Datasheet > HD74ALVCH162501

HD74ALVCH162501

更新时间： 2024-11-08 22:55:03

品牌	Logo	应用领域
日立 - HITACHI		总线收发器
页数	文件大小	规格书
13页	55K
描述
18-bit Universal Bus Transceivers with 3-state Outputs

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HD74ALVCH162501 数据手册

HD74ALVCH162501

18-bit Universal Bus Transceivers with 3-state Outputs

ADE-205-182 (Z)

Preliminary

1st. Edition

December 1996

Description

Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB

and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the

transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at

a high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the low to

high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the

outputs are in the high impedance state. Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high, and

OEBA is active low). Active bus hold circuitry is provided to hold unused or floating data inputs at a

valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce

overshoot and undershoot.

Features

•

V_CC= 2.3 V to 3.6 V

Typical V_OLground bounce < 0.8 V (@V_CC= 3.3 V, Ta = 25°C)

Typical V_OHundershoot > 2.0 V (@V_CC= 3.3 V, Ta = 25°C)

High output current ±12 mA (@V_CC= 3.0 V)

Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

All outputs have equivalent 26 Ω series resistors, so no external resistors are required.

12 3 4 5 6 7...13

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型号	品牌	获取价格	描述	数据表
HD74ALVCH162501T	HITACHI	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
HD74ALVCH162501T	RENESAS	获取价格	ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, TSSOP-56
HD74ALVCH162501TEL	HITACHI	获取价格	Registered Bus Transceiver, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
HD74ALVCH162543	HITACHI	获取价格	16-bit Registered Transceivers with 3-state Outputs
HD74ALVCH162543T	HITACHI	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, T
HD74ALVCH162543T	RENESAS	获取价格	ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, TSSOP-56
HD74ALVCH162543TEL	HITACHI	获取价格	暂无描述
HD74ALVCH16260	HITACHI	获取价格	12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
HD74ALVCH16260T	HITACHI	获取价格	Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TTP-56D
HD74ALVCH16260T	RENESAS	获取价格	ALVC/VCX/A SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56, TTP-56D