Datasheet > HD49783FP

HD49783FP

更新时间： 2024-02-03 23:59:36

品牌	Logo	应用领域
日立 - HITACHI		光电二极管商用集成电路
页数	文件大小	规格书
8页	732K
描述
Consumer Circuit, PDSO16, PLASTIC, SOP-16

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技术参数
数据手册

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HD49783FP 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	16
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.7	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDSO-G16	长度：	10.06 mm
端子数量：	16	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
座面最大高度：	2.2 mm	表面贴装：	YES
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	5.5 mm
Base Number Matches：	1

HD49783FP 数据手册

HD49783

Block Diagram

V_CC

DA8

DA7

DA6

DA5

DA4

DA3

DA2

MRS

SDA

Tail mark

counter

Hold signal

Address

shift

Clock

gate

SCL

Data

shift

Address

decoder

AD1

AD2

AD3

Output

latch

DA1

GND

Functional Description

The Synchronized Serial Bus (SSB)

Hold Mode: The IC enters hold mode on the

second fall of the SDA signal, and data is held in

the IC internal shift register until it switches to

Latch mode.

• This communications technique uses two lines:

the SCL (serial clock) and the SDA (serial

data).

Latch Mode: The IC enters latch mode on the

third fall of the SDA signal, and the data is output

from the IC internal shift register to the IC's

control register.

• Data consists of an 8 bit address field and a data

field of arbitrary length. The length of the data

field is determined by the receiving IC.

The combination of the hold and latch modes

allows synchronization with multiple other ICs

using one IC and only one instruction.

• The data is acquired by shift registers internal to

the ICs connected to the SSB, and is determined

as described below by the state of the SDA

counter, which increments on the fall of the

SDA signal. Note that the SDA counter

operates while the SCL is at the high level, and

is reset when the SCL is at a low level.

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