Datasheet > HCS573MS

HCS573MS

更新时间： 2023-12-20 18:44:57

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
10页	440K
描述
CMOS Octal Transparent Latch, Three-State

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数据手册

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HCS573MS 数据手册

DATASHEET

HCS573MS

Radiation Hardened Octal Transparent Latch, Three-State

FN4056

Rev 0.00

September 1995

Features

• 3 Micron Radiation Hardened SOS CMOS

Pinouts

20 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T20, LEAD FINISH C

TOP VIEW

• Total Dose 200K RAD (Si)

• SEP Effective LET No Upsets: >100 MEV-cm²/mg

• Single Event Upset (SEU) Immunity < 2 x 10^-9Errors/

Bit-Day (Typ)

VCC

• Dose Rate Survivability: >1 x 10¹²RAD (Si)/s

• Dose Rate Upset >10¹⁰RAD (Si)/s 20ns Pulse

• Latch-Up Free Under Any Conditions

• Fanout (Over Temperature Range)

- Bus Driver Outputs - 15 LSTTL Loads

• Military Temperature Range: -55^oC to +125^oC

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

18 Q1

17 Q2

16 Q3

13 Q6

GND 10

11 LE

- VIL = 0.3 VCC Max

- VIH = 0.7 VCC Min

• Input Current Levels Ii  5A at VOL, VOH

20 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP4-F20, LEAD FINISH C

TOP VIEW

Description

The Intersil HCS573MS is a Radiation Hardened octal trans-

parent three-state latch with an active low output enable.

The HCS573MS utilizes advanced CMOS/SOS technology.

The outputs are transparent to the inputs when the Latch

Enable (LE) is HIGH. When the Latch Enable (LE) goes

LOW, the data is latched. The Output Enable (OE) controls

the tri-state outputs. When the Output Enable (OE) is HIGH,

the outputs are in the high impedance state. The latch oper-

ation is independent of the state of the Output Enable.

VCC

The HCS573MS utilizes advanced CMOS/SOS technology

to achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

GND

The HCS573MS is supplied in a 20 lead Ceramic

flatpack (K suffix) or a SBDIP Package (D suffix).

Ordering Information

PART NUMBER

HCS573DMSR

TEMPERATURE RANGE

-55^oC to +125^oC

+25^oC

SCREENING LEVEL

Intersil Class S Equivalent

Sample

PACKAGE

20 Lead SBDIP

HCS573KMSR

20 Lead Ceramic Flatpack

20 Lead SBDIP

HCS573D/Sample

HCS573K/Sample

HCS573HMSR

+25^oC

Sample

20 Lead Ceramic Flatpack

Die

+25^oC

Die

FN4056 Rev 0.00

September 1995

Page 1 of 10

12 3 4 5 6 7...10

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与HCS573MS相关器件

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HCS5HXB37C15	VECTRON	获取价格	Temperature Compensated Crystal Oscillators
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HCS74D	INTERSIL	获取价格	Radiation Hardened Dual-D Flip-Flop with Set and Reset
HCS74DMSR	INTERSIL	获取价格	Radiation Hardened Dual-D Flip-Flop with Set and Reset
HCS74DTR	INTERSIL	获取价格	Radiation Hardened Dual-D Flip-Flop with Set and Reset
HCS74HMSR	INTERSIL	获取价格	Radiation Hardened Dual-D Flip-Flop with Set and Reset
HCS74K	INTERSIL	获取价格	Radiation Hardened Dual-D Flip-Flop with Set and Reset
HCS74K/SAMPLE	RENESAS	获取价格	HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERA
HCS74KMSH	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,D TYPE,CMOS, RAD HARD,FP,14PIN,CERAMIC
HCS74KMSR	INTERSIL	获取价格	Radiation Hardened Dual-D Flip-Flop with Set and Reset

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