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HCPL2611VM

更新时间: 2024-11-06 18:44:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 输出元件光电
页数 文件大小 规格书
18页 3353K
描述
Logic IC Output Optocoupler, 1-Element, 5000V Isolation, 10MBps, LEAD FREE, DIP-8

HCPL2611VM 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LEAD FREE, DIP-8Reach Compliance Code:compliant
HTS代码:8541.40.80.00风险等级:5.66
其他特性:CMOS COMPATIBLE, UL RECOGNIZED, VDE APPROVED配置:SINGLE
标称数据速率:10 MBps最大正向电流:0.05 A
最大绝缘电压:5000 V元件数量:1
最大通态电流:0.05 A最高工作温度:100 °C
最低工作温度:-40 °C光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER
最小供电电压:4.5 VBase Number Matches:1

HCPL2611VM 数据手册

 浏览型号HCPL2611VM的Datasheet PDF文件第2页浏览型号HCPL2611VM的Datasheet PDF文件第3页浏览型号HCPL2611VM的Datasheet PDF文件第4页浏览型号HCPL2611VM的Datasheet PDF文件第5页浏览型号HCPL2611VM的Datasheet PDF文件第6页浏览型号HCPL2611VM的Datasheet PDF文件第7页 
April 2013  
Single-Channel: 6N137M, HCPL2601M, HCPL2611M  
Dual-Channel: HCPL2630M, HCPL2631M  
High-Speed 10 MBit/s Logic Gate Optocouplers  
Features  
Description  
Very High Speed – 10 MBit/s  
Superior CMR – 10 kV/µs  
Fan-out of 8 Over -40°C to +85°C  
Logic Gate Output  
Strobable Output  
Wired OR-open Collector  
U.L. Recognized (File # E90700, Vol. 2)  
The 6N137M, HCPL2601M, HCPL2611M single-channel  
and HCPL2630M, HCPL2631M dual-channel optocou-  
plers consist of a 850 nm AlGaAS LED, optically coupled  
to a very high speed integrated photo-detector logic gate  
with a strobable output. This output features an open col-  
lector, thereby permitting wired OR outputs. The  
switching parameters are guaranteed over the tempera-  
ture range of -40°C to +85°C. A maximum input signal of  
5 mA will provide a minimum output sink current of  
13 mA (fan out of 8).  
Applications  
Ground Loop Elimination  
LSTTL to TTL, LSTTL or 5 V CMOS  
Line Receiver, Data Transmission  
Data Multiplexing  
Switching Power Supplies  
Pulse Transformer Replacement  
Computer-peripheral Interface  
An internal noise shield provides superior common  
mode rejection of typically 10 kV/µs. The HCPL2601M  
and HCPL2631M has a minimum CMR of 5 kV/µs. The  
HCPL2611M has a minimum CMR of 10 kV/µs.  
Schematics  
Package Outlines  
8
8
VCC  
N/C  
+
1
8
VCC  
+
1
8
1
1
VF1  
_
VE  
2
3
7
6
5
V01  
2
3
7
6
5
VF  
_
8
8
_
VO  
V02  
1
1
VF2  
Figure 2. Package Options  
Truth Table (Positive Logic)  
GND  
N/C  
4
GND  
+
4
Input  
Enable  
Output  
H
L
H
H
L
H
H
H
L
6N137M  
HCPL2601M  
HCPL2611M  
HCPL2630M  
HCPL2631M  
(Preliminary)  
H
L
L
L
(1)  
A 0.1µF bypass capacitor must be connected between pins 8 and 5  
.
H
L
NC  
NC  
Figure 1. Schematics  
H
©2009 Fairchild Semiconductor Corporation  
6N137M, HCPL26XXM Rev. 1.0.8  
www.fairchildsemi.com  

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