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HCPL-7723-300 PDF预览

HCPL-7723-300

更新时间: 2024-11-04 20:20:19
品牌 Logo 应用领域
安华高科 - AVAGO 输出元件光电
页数 文件大小 规格书
12页 225K
描述
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.300 INCH, SURFACE MOUNT, DIP-8

HCPL-7723-300 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active包装说明:0.300 INCH, SURFACE MOUNT, DIP-8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8541.40.80.00Factory Lead Time:26 weeks
风险等级:5.24Is Samacsys:N
其他特性:UL RECOGNIZED配置:COMPLEX
最大绝缘电压:3750 VJESD-609代码:e0
安装特点:SURFACE MOUNT元件数量:1
最大通态电流:0.01 A最高工作温度:85 °C
最低工作温度:-40 °C光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER
最大功率耗散:0.6 W标称响应时间:2.2e-8 ns
子类别:Optocoupler - IC Outputs最小供电电压:4.5 V
标称供电电压:5.5 V表面贴装:YES
端子面层:Tin/Lead (Sn/Pb)Base Number Matches:1

HCPL-7723-300 数据手册

 浏览型号HCPL-7723-300的Datasheet PDF文件第2页浏览型号HCPL-7723-300的Datasheet PDF文件第3页浏览型号HCPL-7723-300的Datasheet PDF文件第4页浏览型号HCPL-7723-300的Datasheet PDF文件第5页浏览型号HCPL-7723-300的Datasheet PDF文件第6页浏览型号HCPL-7723-300的Datasheet PDF文件第7页 
HCPL-7723/0723  
50 MBd 2 ns PWD High Speed CMOS Optocoupler  
Data Sheet  
Lead (Pb) Free  
RoHS 6 fully  
compliant  
RoHS 6 fully compliant options available;  
-xxxE denotes a lead-free product  
Description  
Features  
• +5 V CMOS compatibility  
• High speed: 50 MBd min.  
• 2 ns max. pulse width distortion  
• 22 ns max. prop. delay  
Available in either 8-pin DIP or SO-8 package style respec-  
tively, the HCPL-7723 or HCPL-0723 optocoupler utilize  
the latest CMOS IC technology to achieve outstanding  
speed performance of minimum 50 MBd data rate and  
2ns maximum pulse width distortion.  
• 16 ns max. prop. delay skew  
• 10 kV/µs min. common mode rejection  
• –40 to 85°C temperature range  
• Safety and regulatory approvals:  
Basic building blocks of HCPL-7723/0723 are a CMOS  
LED driver IC, a high speed LED and a CMOS detector  
IC. A CMOS logic input signal controls the LED driver  
IC, which supplies current to the LED. The detector  
IC incorporates an integrated photodiode, a high speed  
transimpedance amplifier, and a voltage comparator with  
an output driver.  
UL recognized  
– 5000 V for 1 min. per UL1577 for HCPL-7723 for  
rms  
option 020  
– 3750 V for 1 min. per UL1577 for HCPL-0723  
rms  
CSA component acceptance notice #5  
Functional Diagram  
IEC/EN/DIN EN 60747-5-5  
– V  
– V  
= 630 V  
= 567 V  
for HCPL-7723 option 060  
for HCPL-0723 option 060  
iorm  
peak  
iorm  
peak  
**V  
1
2
8
7
V
**  
DD2  
DD1  
V
I
NC*  
Applications  
I
O
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,  
SDS, Isolated A/D or D/A conversion  
3
4
6
5
NC*  
V
O
LED1  
• Multiplexed data transmission  
• High speed digital input/output  
• Computer peripheral interface  
• Microprocessor system interface  
GND  
GND  
2
1
SHIELD  
*
PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT  
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.  
PIN 7 IS NOT CONNECTED INTERNALLY.  
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN  
PINS 1 AND 4, AND 5 AND 8.  
TRUTH TABLE  
(POSITIVE LOGIC)  
V , INPUT  
I
LED1  
V
, OUTPUT  
O
H
L
OFF  
ON  
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly of  
this component to prevent damage and/or degradation, which may be induced by ESD.  

HCPL-7723-300 替代型号

型号 品牌 替代类型 描述 数据表
HCPL-7723-300E AVAGO

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