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HCPL-7723-520E PDF预览

HCPL-7723-520E

更新时间: 2024-11-24 12:04:39
品牌 Logo 应用领域
安华高科 - AVAGO 光电输出元件
页数 文件大小 规格书
12页 196K
描述
50 MBd 2 ns PWD High Speed CMOS Optocoupler

HCPL-7723-520E 数据手册

 浏览型号HCPL-7723-520E的Datasheet PDF文件第2页浏览型号HCPL-7723-520E的Datasheet PDF文件第3页浏览型号HCPL-7723-520E的Datasheet PDF文件第4页浏览型号HCPL-7723-520E的Datasheet PDF文件第5页浏览型号HCPL-7723-520E的Datasheet PDF文件第6页浏览型号HCPL-7723-520E的Datasheet PDF文件第7页 
HCPL-7723/0723  
50 MBd 2 ns PWD High Speed CMOS Optocoupler  
Data Sheet  
Lead (Pb) Free  
RoHS 6 fully  
compliant  
RoHS 6 fully compliant options available;  
-xxxE denotes a lead-free product  
Description  
Features  
• +5 V CMOS compatibility  
• High speed: 50 MBd min.  
• 2 ns max. pulse width distortion  
• 22 ns max. prop. delay  
Available in either 8-pin DIP or SO-8 package style respec-  
tively, the HCPL-7723 or HCPL-0723 optocoupler utilize  
the latest CMOS IC technology to achieve outstanding  
speed performance of minimum 50 MBd data rate and  
2ns maximum pulse width distortion.  
• 16 ns max. prop. delay skew  
• 10 kV/µs min. common mode rejection  
• –40 to 85°C temperature range  
• Safety and regulatory approvals:  
Basic building blocks of HCPL-7723/0723 are a CMOS  
LED driver IC, a high speed LED and a CMOS detector  
IC. A CMOS logic input signal controls the LED driver  
IC, which supplies current to the LED. The detector  
IC incorporates an integrated photodiode, a high speed  
transimpedance amplifier, and a voltage comparator with  
an output driver.  
UL recognized  
– 5000 V for 1 min. per UL1577 for HCPL-7723 for  
rms  
option 020  
– 3750 V for 1 min. per UL1577 for HCPL-0723  
rms  
CSA component acceptance notice #5  
Functional Diagram  
IEC/EN/DIN EN 60747-5-5  
– V  
– V  
= 630 V  
= 567 V  
for HCPL-7723 option 060  
for HCPL-0723 option 060  
iorm  
peak  
iorm  
peak  
**V  
1
2
8
7
V
**  
DD2  
DD1  
V
I
NC*  
Applications  
I
O
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,  
SDS, Isolated A/D or D/A conversion  
3
4
6
5
NC*  
V
O
LED1  
• Multiplexed data transmission  
• High speed digital input/output  
• Computer peripheral interface  
• Microprocessor system interface  
GND  
GND  
2
1
SHIELD  
*
PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT  
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.  
PIN 7 IS NOT CONNECTED INTERNALLY.  
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN  
PINS 1 AND 4, AND 5 AND 8.  
TRUTH TABLE  
(POSITIVE LOGIC)  
V , INPUT  
I
LED1  
V
, OUTPUT  
O
H
L
OFF  
ON  
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly of  
this component to prevent damage and/or degradation, which may be induced by ESD.  

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