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HCPL-7721-560 PDF预览

HCPL-7721-560

更新时间: 2024-11-24 21:05:15
品牌 Logo 应用领域
安华高科 - AVAGO 输出元件光电
页数 文件大小 规格书
19页 279K
描述
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 25Mbps, 0.300 INCH, LEAD FREE, SURFACE MOUNT, DIP-8

HCPL-7721-560 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active包装说明:0.300 INCH, LEAD FREE, SURFACE MOUNT, DIP-8
Reach Compliance Code:compliantHTS代码:8541.40.80.00
风险等级:5.4其他特性:UL RECOGNIZED, VDE APPROVED
配置:COMPLEX标称数据速率:25 MBps
最大正向电流:0.00001 A最大绝缘电压:3750 V
JESD-609代码:e0安装特点:SURFACE MOUNT
元件数量:1最大通态电流:0.01 A
最高工作温度:85 °C最低工作温度:-40 °C
光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER标称响应时间:4e-8 ns
子类别:Optocoupler - IC Outputs最小供电电压:4.5 V
标称供电电压:5.5 V表面贴装:YES
端子面层:Tin/Lead (Sn/Pb)Base Number Matches:1

HCPL-7721-560 数据手册

 浏览型号HCPL-7721-560的Datasheet PDF文件第2页浏览型号HCPL-7721-560的Datasheet PDF文件第3页浏览型号HCPL-7721-560的Datasheet PDF文件第4页浏览型号HCPL-7721-560的Datasheet PDF文件第5页浏览型号HCPL-7721-560的Datasheet PDF文件第6页浏览型号HCPL-7721-560的Datasheet PDF文件第7页 
HCPL-0720/7720/0721/7721  
40 ns Propagation Delay, CMOS Optocoupler  
Data Sheet  
Lead (Pb) Free  
RoHS 6 fully  
compliant  
RoHS 6 fully compliant options available;  
-xxxE denotes a lead-free product  
Description  
Features  
ꢀ+5ꢀVꢀCMOSꢀcompatibility  
ꢀ20ꢀnsꢀmaximumꢀprop.ꢀdelayꢀskew  
ꢀHighꢀspeed:ꢀ25ꢀMBd  
ꢀ40ꢀnsꢀmax.ꢀprop.ꢀdelay  
ꢀ10ꢀkV/µsꢀminimumꢀcommonꢀmodeꢀrejection  
ꢀ–40ꢀtoꢀ85°Cꢀtemperatureꢀrange  
Availableꢀ inꢀ eitherꢀ anꢀ 8-pinꢀ DIPꢀ orꢀ SO-8ꢀ packageꢀ styleꢀ  
respectively,ꢀtheꢀHCPL-772XꢀorꢀHCPL-072Xꢀoptocouplersꢀ  
utilizeꢀ theꢀ latestꢀ CMOSꢀ ICꢀ technologyꢀ toꢀ achieveꢀ out-  
standingꢀ performanceꢀ withꢀ veryꢀ lowꢀ powerꢀ consump-  
tion.ꢀTheHCPL-772X/072Xrequireonlytwobypassca-  
pacitorsꢀforꢀcompleteꢀCMOSꢀcompatability.ꢀ  
BasicꢀbuildingꢀblocksꢀofꢀtheꢀHCPL-772X/072XꢀareꢀaꢀCMOSꢀ  
LEDdriverIC,ahighspeedLEDandaCMOSdetectorꢀ  
IC.ꢀAꢀCMOSꢀlogicꢀinputꢀsignalꢀcontrolsꢀtheꢀLEDꢀdriverꢀICꢀ  
whichꢀsuppliesꢀcurrentꢀtoꢀtheꢀLED.ꢀTheꢀdetectorꢀICꢀincor-  
poratesꢀ anꢀ integratedꢀ photodiode,ꢀ aꢀ high-speedꢀ tran-  
simpedanceꢀamplifier,ꢀandꢀaꢀvoltageꢀcomparatorꢀwithꢀanꢀ  
outputꢀdriver.  
ꢀSafetyꢀandꢀregulatoryꢀapprovalsꢀꢀ  
ULꢀrecognizedꢀ  
ꢀꢀꢀ–ꢀ3750ꢀVrmsꢀforꢀ1ꢀmin.ꢀperꢀULꢀ1577ꢀ  
ꢀꢀꢀ–ꢀ5000ꢀVrmsꢀforꢀ1ꢀmin.ꢀperꢀULꢀ1577ꢀ  
ꢀꢀꢀꢀꢀꢀꢀ(forꢀHCPL-772Xꢀoptionꢀ020)ꢀ ꢀ  
ꢀ CSAꢀcomponentꢀacceptanceꢀnoticeꢀ#5ꢀ  
IEC/EN/DINꢀENꢀ60747-5-2ꢀ  
ꢀꢀꢀ–ꢀVIORMꢀ=ꢀ630ꢀVpeakꢀforꢀHCPL-772Xꢀoptionꢀ060ꢀ ꢀ  
ꢀꢀꢀ–ꢀVIORMꢀ=ꢀ560ꢀVpeakꢀforꢀHCPL-072Xꢀoptionꢀ060  
Functional Diagram  
Applications  
**V  
1
2
8
7
V
**  
DD2  
DD1  
ꢀDigitalꢀfieldbusꢀisolation:ꢀCC-Link,ꢀDeviceNet,ꢀProfi-  
bus,ꢀSDS  
V
NC*  
I
ꢀACꢀplasmaꢀdisplayꢀpanelꢀlevelꢀshifting  
ꢀMultiplexedꢀdataꢀtransmission  
ꢀComputerꢀperipheralꢀinterface  
ꢀMicroprocessorꢀsystemꢀinterface  
I
O
3
4
6
5
*
V
O
LED1  
GND  
GND  
2
1
SHIELD  
*ꢀ Pinꢀ3ꢀisꢀtheꢀanodeꢀofꢀtheꢀinternalꢀLEDꢀandꢀmustꢀbeꢀleftꢀunconnectedꢀ  
forꢀ guaranteedꢀ dataꢀ sheetꢀ performance.ꢀ Pinꢀ 7ꢀ isꢀ notꢀ connectedꢀ  
internally.ꢀ  
**ꢀ Aꢀ0.1ꢀµFꢀbypassꢀcapacitorꢀmustꢀbeꢀconnectedꢀbetweenꢀpinsꢀ1ꢀandꢀ  
4,ꢀandꢀ5ꢀandꢀ8.  
TRUTH TABLE  
POSITIVE LOGIC  
VI  
H
L
LED1  
OFF  
ON  
Vo OUTPUT  
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly  
of this component to prevent damage and/or degradation which may be induced by ESD.  

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