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HCPL-7710#500 PDF预览

HCPL-7710#500

更新时间: 2024-11-04 19:44:39
品牌 Logo 应用领域
安华高科 - AVAGO 输出元件光电
页数 文件大小 规格书
17页 272K
描述
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 12.5Mbps, 0.300 INCH, SURFACE MOUNT, DIP-8

HCPL-7710#500 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active包装说明:0.300 INCH, SURFACE MOUNT, DIP-8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8541.40.80.00Factory Lead Time:17 weeks
风险等级:5.19其他特性:UL RECOGNIZED
配置:SINGLE标称数据速率:12.5 MBps
最大正向电流:0.01 A最大绝缘电压:3750 V
JESD-609代码:e0安装特点:SURFACE MOUNT
元件数量:1最大通态电流:0.01 A
最高工作温度:100 °C最低工作温度:-40 °C
光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER最长响应时间:0.001 s
子类别:Optocoupler - Transistor Outputs最小供电电压:4.5 V
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
Base Number Matches:1

HCPL-7710#500 数据手册

 浏览型号HCPL-7710#500的Datasheet PDF文件第2页浏览型号HCPL-7710#500的Datasheet PDF文件第3页浏览型号HCPL-7710#500的Datasheet PDF文件第4页浏览型号HCPL-7710#500的Datasheet PDF文件第5页浏览型号HCPL-7710#500的Datasheet PDF文件第6页浏览型号HCPL-7710#500的Datasheet PDF文件第7页 
HCPL-7710/0710  
40 ns Propagation Delay, CMOS Optocoupler  
Data Sheet  
Lead (Pb) Free  
RoHS 6 fully  
compliant  
RoHS 6 fully compliant options available;  
-xxxE denotes a lead-free product  
Description  
Features  
Available in either an 8-pin DIP or SO-8 package style  
respectively, the HCPL-7710 or HCPL-0710 optocouplers  
utilizethelatestCMOSICtechnologytoachieveoutstand-  
ing performance with very low power consumption. The  
HCPL-x710requireonlytwobypasscapacitorsforcomplete  
CMOS compatibility.  
+5 V CMOS compatibility  
8 ns maximum pulse width distortion  
20 ns maximum prop. delay skew  
High speed: 12 Mbd  
40 ns maximum prop. delay  
10 kV/µs minimum common mode rejection  
-40°C to 100°C temperature range  
Basic building blocks of the HCPL-x710 are a CMOS LED  
driver IC, a high speed LED and a CMOS detector IC. A  
CMOS logic input signal controls the LED driver IC, which  
supplies current to the LED. The detector IC incorporates  
an integrated photodiode, a high-speed transimpedance  
amplifier,andavoltagecomparatorwithanoutputdriver.  
Safety and regulatory approvals  
UL Recognized  
3750 Vrms for 1 min. per UL 1577  
5000 Vrms for 1 min. per UL 1577 (for HCPL-7710  
option 020)  
CSA Component Acceptance Notice #5  
IEC/EN/DIN EN 60747-5-5  
Functional Diagram  
– VIORM = 630 Vpeak for HCPL-7710 Option 060  
– VIORM = 567 Vpeak for HCPL-0710 Option 060  
1
2
8
7
**V  
V
**  
DD1  
DD2  
Applications  
NC*  
V
I
Digital fieldbus isolation: DeviceNet, SDS, Profibus  
AC plasma display panel level shifting  
Multiplexed data transmission  
Computer peripheral interface  
Microprocessor system interface  
I
O
3
4
6
5
NC*  
V
O
LED1  
GND  
GND  
2
1
SHIELD  
* Pin 3 is the anode of the internal LED and must be left  
unconnected for guaranteed data sheet performance.  
Pin 7 is not connected internally.  
** A 0.1 µF bypass capacitor must be connected  
between pins 1 and 4, and 5 and 8.  
TRUTH TABLE  
(POSITIVE LOGIC)  
V , INPUT  
I
LED1 V , OUTPUT  
O
H
L
OFF  
ON  
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly  
of this component to prevent damage and/or degradation which may be induced by ESD.  

HCPL-7710#500 替代型号

型号 品牌 替代类型 描述 数据表
HCPL-7710-500E AVAGO

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