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HCF4517 PDF预览

HCF4517

更新时间: 2024-11-03 23:54:59
品牌 Logo 应用领域
其他 - ETC 移位寄存器
页数 文件大小 规格书
8页 323K
描述
DUAL 64-STAGE STATIC SHIFT REGISTER

HCF4517 数据手册

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HCF4517B  
DUAL 64 STAGE STATIC SHIFT REGISTER  
CLOCK FREQUENCY 12MHz (Typ.)  
at V = 10V  
DD  
SCHMITT TRIGGER CLOCK INPUTS  
ALLOWS OPERATION WITH VERY SLOW  
CLOCK RISE AND FALL TIMES  
THREE STATE OUTPUTS  
QUIESCENT CURRENT SPECIFIED UP TO  
20V  
DIP  
STANDARDIZED, SYMMETRICAL OUTPUT  
CHARACTERISTCS  
ORDER CODES  
PACKAGE  
5V, 10V AND 15V PARAMETRIC RATINGS  
INPUT LEAKAGE CURRENT  
TUBE  
T & R  
DIP  
HCF4517BEY  
HCF4517BM1  
I = 100nA (MAX) AT V = 18V T = 25°C  
I
DD  
A
SOP  
HCF4517M013TR  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALL REQUIREMENTS OF JEDEC  
JESD13B "STANDARD SPECIFICATIONS  
FOR DESCRIPTION OF B SERIES CMOS  
DEVICES"  
32nd, 48th, and 64th stages. These stages also  
serve as input points allowing data to be put in at  
the 17th , 33rd, and 49th stages when the write  
enable input is a logic 1 and the clock goes  
through a low to high transition. The truth table  
indicates how the clock and write enable inputs  
control the operation of HCF4517B. Inputs at the  
intermediate stages allow entry of 64-bits into the  
register with 16 clock pulses. The 3-state outputs  
permit connection of this device to an external  
bus.  
DESCRIPTION  
HCF4517B is a monolithic integrated circuit  
fabricated in Metal Oxide Semiconductor  
technology available in DIP package.  
This device is a dual 64-stage static shift register  
consisting of two independent registers each  
having a clock, data, and write enable input and  
outputs accessible by stages following the 16th,  
PIN CONNECTION  
September 2002  
1/8  

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