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HCF4518BF PDF预览

HCF4518BF

更新时间: 2024-11-03 22:55:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器逻辑集成电路
页数 文件大小 规格书
14页 324K
描述
DUAL UP-COUNTERS

HCF4518BF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
Is Samacsys:N计数方向:UP
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:DECADE COUNTER最大频率@ Nom-Sup:1500000 Hz
最大I(ol):0.00036 A工作模式:SYNCHRONOUS
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5/15 V
认证状态:Not Qualified子类别:Counters
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

HCF4518BF 数据手册

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HCC/HCF4518B  
HCC/HCF4520B  
DUAL UP-COUNTERS  
HCC/HCF4518B DUAL BCD UP-COUNTER  
HCC/HCF4520B DUAL BINARY UP-  
COUNTER  
.
.
.
.
MEDIUM-SPEED OPERATION – 6MHz TYP.  
CLOCK FREQUENCY AT 10V  
POSITIVE - OR NEGATIVE - EDGE TRIGGER-  
EY  
F
ING  
(Plastic Package)  
(Ceramic Frit Seal Package)  
SYNCHRONOUS INTERNAL CARRY PROPA-  
GATION  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
.
.
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVESTANDARDN°13A, ”STANDARD SPE-  
CIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
M1  
C1  
(Micro Package)  
(Plastic Chip Carrier)  
ORDER CODES :  
.
.
HCC45XXBF  
HCF45XXBEY  
HCF45XXBM1  
HCF45XXBC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4518B/4520B (extended temperature  
range) and HCF4518B/4520B (intermediate tem-  
perature range) are monolithic integrated circuits,  
available in 16-lead dual in-line plastic or ceramic  
package and plastic micro package. The  
HCC/HCF4518B Dual BCD Up Counter and  
HCC/HCF4520B DualBinary Up Counter each con-  
sist of two identical, internally synchronous 4-stage  
counters. The counter stages are D-type flip-flops  
having interchangeable Clock and Enable lines for  
incrementing on either the positive-going or nega-  
tive-going transition. For single-unit operation the  
Enable input is maintained ”high” and the counter  
advances on each positive-going transition of the  
Clock. The counters are cleared by high levels on  
their Reset lines. The counter can be cascaded in  
the ripple mode by connecting Q4 to the enable  
input of the subsequent counter while the clockinput  
of the latter is held low.  
June 1989  
1/14  

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