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HCF4076BC1 PDF预览

HCF4076BC1

更新时间: 2024-11-03 22:20:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路输出元件
页数 文件大小 规格书
13页 292K
描述
4 BIT D TYPE REGISTERS

HCF4076BC1 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
Is Samacsys:N其他特性:WITH HOLD MODE; WITH DUAL OUTPUT ENABLE
系列:4000/14000/40000JESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.965 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:3000000 Hz位数:4
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/15 V传播延迟(tpd):600 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.965 mm
最小 fmax:8 MHzBase Number Matches:1

HCF4076BC1 数据手册

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HCC4076B  
HCF4076B  
4 BIT D TYPE REGISTERS  
.
.
THREE STATE OUTPUTS  
INPUT DISABLE WITHOUT GATING THE  
CLOCK  
GATED OUTPUT CONTROL LINES FOR EN-  
ABLING OR DISABLING THE OUTPUTS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
5V, 10V AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25oC  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD N. 13A, ” STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF B  
SERIES CMOS DEVICES ”  
.
.
.
.
EY  
F
(Plastic Package)  
(Ceramic Package)  
.
.
M1  
C1  
(Micro Package)  
(Chip Carrier)  
ORDER CODES :  
HCC4076BF  
HCF4076BEY  
HCF4076BM1  
HCF4076BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4076B (extended temperature range) and  
HCC4076B (intermediate temperature range) are  
monolithic integrated circuit, available in 16 lead  
dual in line plastic or ceramic package and plastic  
micropackage.  
The HCC/HCF4076B types are four-bit registers  
consisting of D-type flip-flops that feature three-  
state outputs. Data Disable inputs are provided to  
controltheentryof data into theflip-flops. Whenboth  
Data Disable inputs are low, data at the D inputs are  
loaded into their respective flip-flops on the next  
positive transition of the click input. Output Disable  
inputs are also provided. When the Output Disable  
inputs are both low, the normal logic states of the  
four outputs are available to the load. The outputs  
are disabled independently of the clock by a high  
logic level at either Output Disable input, and pres-  
ent a high impedance.  
September 1988  
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