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HCC40104B PDF预览

HCC40104B

更新时间: 2024-11-18 22:33:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
12页 256K
描述
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

HCC40104B 数据手册

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HCC/HCF40104B  
HCC/HCF40194B  
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER  
.
MEDIUM-SPEED OPERATION : fCL = 9MHz  
(typ.) @ VDD = 10V  
FULLY STATIC OPERATION  
SYNCHRONOUS PARALLEL OR SERIAL  
OPERATION  
.
.
.
.
THREE-STATE OUTPUTS (HCC/HCF40104B)  
EY  
F
ASYNCHRONOUS  
MASTER  
RESET  
(Plastic Package)  
(Ceramic Package)  
(HCC/HCF40194B)  
STANDARDIZED, SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT AT 20V FOR HCC DE-  
VICE  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVESTANDARDN°13A, ”STANDARD SPE-  
CIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
.
.
C1  
(Plastic Chip Carrier )  
.
.
ORDER CODES :  
HCC401XXBF  
HCF401XXBEY  
HCF401XXBC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC40104B, HCC40194B, (extended tem-  
perature range) and the HCC40104B, HCF40194B  
(intermediate temperature range) are monolithic in-  
tegrated circuits, available in 16-lead dual in-line  
plastic or ceramic package and plastic micro pack-  
age. The HCC/HCF 40104B is a universal shift reg-  
isterfeaturing parallel inputs, parallel outputs, SHIFT  
RIGHTand SHIFTLEFT serial inputs, and a high-im-  
pedance third output state allowing the device to be  
used in bus-organized systems. In the parallel-load  
mode (S0 and S1 are high), data is loaded into the  
associated flip-flop and appears at the output after  
the positive transition of the CLOCK input. During  
loading, serial data flow is inhibited. Shift-right and  
shift-left are accomplished synchronously on the  
positive clock edge with serial data entered at the  
SHIFT RIGHT and SHIFT LEFT serial inputs, re-  
spectively. Clearing the register is accomplished by  
setting both mode controls low and clocking the reg-  
ister. When the output enable input is low, all outputs  
assume the high impedance state. The  
HCC/HCF40194B is a universal shift register featur-  
ingparallel inputs, parallel outputs SHIFT RIGHTand  
SHIFT LEFT serial inputs, and a direct overriding  
clear input. In the parallel-load mode (S0 and S1 are  
high), data is loaded into the associated flip-flop and  
40104B  
40194B  
June 1989  
1/12  

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