HCC/HCF40109B
QUAD LOW-TO-HIGH VOLTAGE LEVEL SHIFTER
.
INDEPENDENCE OF POWER SUPPLY SE-
controls produces a high-impedance state in the
corresponding output.
QUENCE CONSIDERATIONS – VCC CAN EX-
CEED VDD, INPUT SIGNALS CAN EXCEED
BOTH VCC AND VDD
.
.
.
.
UP AND DOWN LEVEL-SHIFTING CAPA-
BILITY
THREE-STATE OUTPUTS WITH SEPARATE
ENABLE CONTROLS
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALLREQUIREMENTS OF JEDECTEN-
TATIVE STANDARD N°. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
F
(Plastic Package)
(Ceramic Frit Seal Package)
.
.
.
.
C1
C1
(Micro package)
(Plastic Chip Carrier)
ORDER CODES :
HCC40109BF
HCF40109BEY HCF40109BC1
HCF40109BM1
DESCRIPTION
The HCC40109B (extended temperature range)
and HCF40109B (intermediate temperature range)
are monolithic integrated circuits, available in 16-
lead dual in-line plastic or ceramic package and
plastic micropackage. The HCC/HCF40109B con-
tains four low-to-high-voltage level-shifting circuits.
Each circuit will shift a low-voltage digital-logic input
signal (A, B, C, D) with logical 1 = VCC and logical 0
= VSS to a higher-voltage output signal (E, F, G, H)
with logical 1 = VDD and logical 0 = VSS. The
HCC/HCF40109B, unlike other low-to-high level-
shifting circuits, does not require the presence of the
high-voltage supply (VDD) before the application of
either the low-voltage supply (VCC) or the input sig-
nals. There are no restrictions on the sequence of
application of VDD, VCC, or the input signals. In ad-
dition, there are no restrictions on the relative mag-
nitudesodthe supplyvoltagesorinput signals within
PIN CONNECTIONS
the device maximum ratings ; VCC mayexceed VDD
and input signals may exceed VCC, and VDD. When
operated in the mode VCC VDD the
,
,
HCC/HCF40109B, will operate as a high-to-low
level-shifter. The HCC/HCF 40109B also features
individual three-state output capability. A low level
on any of the separately enabled three-state output
June 1989
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