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HCC40105B PDF预览

HCC40105B

更新时间: 2024-11-18 22:33:19
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意法半导体 - STMICROELECTRONICS 先进先出芯片
页数 文件大小 规格书
12页 262K
描述
FIFO REGISTER

HCC40105B 数据手册

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HCC40105B  
HCF40105B  
FIFO REGISTER  
.
INDEPENDENT ASYNCHRONOUS INPUTS  
AND OUTPUTS  
3-STATE OUTPUTS  
EXPANDABLE IN EITHER DIRECTION  
STATUS INDICATORS ON INPUT AND OUT-  
PUT  
RESET CAPABILITY  
STANDARDIZED, SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED AT 20V  
FOR HCC DEVICE  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
READY) indicates if the FIFO contains data. As the  
earliest data are removed from the bottom ofthe data  
stack (the output end), all data entered later will auto-  
matically propagate (ripple) toward the output.  
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EY  
F
(Plastic Package)  
(Ceramic Package)  
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100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD No 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
C1  
(ChipCarrier)  
ORDER CODES :  
HCC40105BF  
HCF40105BEY  
HCF40105BC1  
DESCRIPTION  
The HCC40105B (extended temperature range) and  
HCF40105B (intermediate temperature range) are  
monolithic integratedcircuits, available in16-lead dual  
in-line plastic or ceramic package.  
PIN CONNECTIONS  
The HCC/HCF40105B is a low-power first-in-first-out  
(FIFO)elastic” storage register that can store 164-bit  
words. It is capable of handling input and output data  
atdifferent shiftingrates. This feature makes itparticu-  
larly useful as a buffer between asynchronous sys-  
tems. Each word position in the register is clocked by  
a control flip-flop, which stores a marker bit. A ”1” sig-  
nifiesthat the position’s data is filledand a0” denotes  
a vacancy in that position. The control flip-flop detects  
the state of the preceding flip-flop and communicates  
itsown status tothesucceeding flip-flop.When a con-  
trol flip-flop is in the ”0” state and sees a ”1” in the  
preceding flip-flop, it generates a clock pulse that  
transfers data from the preceding four data latches  
into its own four data latches andresets the preceding  
flip-flop to ”0”. The first and last control flip-flops have  
buffered outputs. Since all empty locations ”bubble”  
automatically to the input end, and all valid data ripple  
through to the output end, the statusof thefirst control  
flip-flop (DATA-IN READY) indicates if the FIFOisfull,  
and the status of the last flip-flop (DATA-OUT  
June 1989  
1/12  

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