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HCC4006BF PDF预览

HCC4006BF

更新时间: 2024-11-18 22:33:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
11页 262K
描述
18-STAGE STATIC SHIFT REGISTER

HCC4006BF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.63
其他特性:SHARED CLOCK BETWEEN 4 SHIFT REGISTERS; TWO 4 BIT & TWO 5 BIT SHIFT REGISTERS计数方向:RIGHT
系列:4000/14000/40000JESD-30 代码:R-GDIP-T14
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:SERIAL IN SERIAL OUT位数:5
功能数量:4端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/18 V
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
Base Number Matches:1

HCC4006BF 数据手册

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HCC/HCF4006B  
18-STAGE STATIC SHIFT REGISTER  
.
PERMANENT REGISTER STORAGE WITH  
CLOCK LINE ”HIGH” OR ”LOW” ... NO INFOR-  
MATION RECIRCULATION REQUIRED  
FULLY STATIC OPERATION  
SHIFTING RATES UP TO 12MHz @ 10V (typ.)  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
INPUT CURRENT OF100nA AT 18V AND 25 °C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
5V, 10V, AND 15V PARAMETRIC RATING  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVESTANDARDN°13A, ”STANDARD SPE-  
CIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
.
F
EY  
.
.
(Ceramic Frit Seal Package)  
(Plastic Package)  
.
.
.
M1  
C1  
(Micro Package)  
(Plastic Chip Carrier)  
ORDER CODES :  
HCC4006BF  
HCF4006BEY  
HCF4006BM1  
HCF4006BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4006B(extended temperature range) and  
the HCF4006B (standard temperature range), are  
monolithic integrated circuits, available in 14-lead  
dual in-line plastic or ceramic package and plastic  
micro package. The types are comprised of 4 sep-  
arate ”shift register” sections ; two sections of four  
stagesand twosections offive stageswith an output  
tap at the fourth stage. Each section has an inde-  
pendent ”single rail” datapath. A commonclock sig-  
nal is used for all stages. Data is shifted to the next  
stage on negative-going transitions of the clock.  
Through appropriate connections of inputs and out-  
puts, multiple register sections of 4, 5, 8, and 9  
stages or single register sections of 10, 12, 13, 14,  
16, 17 and 18 can be implemented using one  
HCC/HCF4006B package. Longer shift register  
sections can be assembled by using more than one  
HCC/HCF4006B. To facilitate cascading stages  
when clock rise and fall times are slow, an optional  
output (D1 + 4’) that is delayed one-half clock-cycle,  
is provided (see truth table for output from pin 2).  
June 1989  
1/11  

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