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HB56U272E-6B PDF预览

HB56U272E-6B

更新时间: 2024-09-26 20:09:03
品牌 Logo 应用领域
日立 - HITACHI 动态存储器内存集成电路
页数 文件大小 规格书
29页 256K
描述
EDO DRAM Module, 2MX72, 60ns, MOS

HB56U272E-6B 数据手册

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HB56U272E-6B/7B/8B  
2,097,152-Word × 72-Bit High Density Dynamic RAM Module  
168-pin JEDEC Standard Outline Buffered 8BYTE DIMM  
Rev.0.0  
Feb.02,1996  
Description  
The HB56U272E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed  
as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56U272E is a 2M x  
72 dynamic RAM module, mounted 9 pieces of 16-Mbit DRAM (HM5117805BTT) sealed in TSOP  
package and 2 pieces of 16-bit BiCMOS line driver (74ABT16244) sealed in TSOP package. The  
HB56U272E offers Extended Data Out(EDO) Page Mode as a high speed access mode. An outline of the  
HB56U272E is 168-pin socket type package (dual lead out). Therefore, the HB56U272E makes high  
density mounting possible without surface mount technology. The HB56U272E provides common data  
inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the its module board.  
Features  
168-pin socket type package (Dual lead out)  
Lead pitch: 1.27 mm  
Single 5 V (±5%) supply  
High speed  
Access time:tRAC = 60/70/80 ns(max.)  
Access time:tCAC = 20/23/25 ns(max.)  
Low power dissipation  
Active mode: 6.01/5.53/5.06 W (max.)  
Standby mode(TTL): 431 mW(max.)  
Buffered input except /RAS and DQ  
4 byte interleave enabled, dual address input (AO/BO)  
EDO page mode capability  
2,048 refresh cycle/32 ms  
2 variations of refresh  
/RAS - only refresh  
/CAS - before -/RAS refresh  
TTL compatible  
Preliminary : This document contains information on a new product. Specifications and information contained herein  
aresubject to change without no tice.  

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