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GVT71512C18TA-5I PDF预览

GVT71512C18TA-5I

更新时间： 2024-01-19 17:46:36
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
29页 424K
描述
Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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GVT71512C18TA-5I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.01 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.51 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GVT71512C18TA-5I 数据手册

 浏览型号GVT71512C18TA-5I的Datasheet PDF文件第2页浏览型号GVT71512C18TA-5I的Datasheet PDF文件第3页浏览型号GVT71512C18TA-5I的Datasheet PDF文件第4页浏览型号GVT71512C18TA-5I的Datasheet PDF文件第6页浏览型号GVT71512C18TA-5I的Datasheet PDF文件第7页浏览型号GVT71512C18TA-5I的Datasheet PDF文件第8页 
CY7C1366A/GVT71256C36  
CY7C1367A/GVT71512C18  
256K × 36 Pin Descriptions  
X36 PBGA Pins  
X36 QFP Pins Name  
Type  
Description  
4P  
4N  
37  
36  
A0  
A1  
A
Input-  
Addresses: These inputs are registered and must meet the set  
Synchronous up and hold times around the rising edge of CLK. The burst  
countergeneratesinternaladdressesassociatedwithA0andA1,  
during burst cycle and wait cycle.  
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32,  
5B, 6B, 2C, 3C, 5C, 100, 99, 82, 81,  
6C, 2R, 6R, 3T, 4T, 44, 45, 46, 47, 48,  
5T  
49, 50  
92 (T/AJ Version)  
43 (TA/A Version)  
5L  
5G  
3G  
3L  
93  
94  
95  
96  
BWa  
Input-  
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for  
BWb Synchronous a READ cycle. BWa controls DQa. BWb controls DQb. BWc  
BWc  
BWd  
controls DQc. BWd controls DQd. Data I/O are high impedance  
if either of these inputs are LOW, conditioned by BWE being  
LOW.  
4M  
4H  
4K  
87  
88  
89  
BWE  
GW  
Input-  
Write Enable: This active LOW input gates byte write operations  
Synchronous and must meet the set-up and hold times around the rising edge  
of CLK.  
Input-  
Global Write: This active LOW input allows a full 36-bit Write to  
Synchronous occur independent of the BWE and BWn lines and must meet the  
set-up and hold times around the rising edge of CLK.  
CLK  
Input-  
Clock: This signal registers the addresses, data, chip enables,  
Synchronous write control, and burst control inputs on its rising edge. All  
synchronous inputs must meet set up and hold times around the  
clock’s rising edge.  
4E  
2B  
98  
97  
CE1  
CE2  
CE3  
OE  
Input-  
Chip Enable: This active LOW input is used to enable the device  
Synchronous and to gate ADSP.  
Input-  
Synchronous device.  
Chip Enable: This active HIGH input is used to enable the  
(not available for  
PBGA)  
92 (for TA/A  
Version only)  
Input-  
Chip Enable:This activeLOWinput is used toenable the device.  
Synchronous Not available for B and T package versions.  
4F  
86  
Input  
Output Enable: This active LOW asynchronous input enables  
the data output drivers.  
4G  
83  
ADV  
Input-  
Address Advance: This active LOW input is used to control the  
Synchronous internal burst counter. A HIGH on this pin generates wait cycle  
(no address advance).  
4A  
4B  
84  
85  
ADSP  
ADSC  
Input-  
Address Status Processor: This active LOW input, along with  
Synchronous CE being LOW, causes a new external address to be registered  
and a READ cycle is initiated using the new address.  
Input-  
Address Status Controller: This active LOW input causes  
Synchronous device to be deselected or selected along with new external  
address to be registered. A Read or Write cycle is initiated  
depending upon write control inputs.  
3R  
7T  
31  
64  
MOD  
E
Input-  
Static  
Mode: This input selects the burst sequence. A LOW on this pin  
selects LinearBurst. ANC orHIGH onthis pinselects Interleaved  
Burst.  
ZZ  
Input-  
Sleep: This active HIGH input puts the device in low power  
Asynchronous consumption standby mode. For normal operation, this input has  
to be either LOW or NC (No Connect).  
(a) 6P, 7P, 7N, 6N, (a) 51, 52, 53, 56, DQa  
6M, 6L, 7L, 6K, 7K, 57, 58, 59, 62, 63 DQb  
(b) 7H, 6H, 7G, 6G, (b) 68, 69, 72, 73, DQc  
6F, 6E, 7E, 7D, 6D, 74, 75, 78, 79, 80 DQd  
(c) 2D, 1D, 1E, 2E, (c) 1, 2, 3, 6, 7, 8,  
Input/  
Output  
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.  
Third Byte is DQc. Fourth Byte is DQd. Input data must meet  
set-up and hold times around the rising edge of CLK.  
2F, 1G, 2G, 1H, 2H,  
9, 12, 13  
(d) 1K, 2K, 1L, 2L, (d) 18, 19, 22, 23,  
2M, 1N, 2N, 1P, 2P 24, 25, 28, 29, 30  
Document #: 38-05264 Rev. *A  
Page 5 of 29  
12345678...29

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与GVT71512C18TA-5I相关器件

型号 品牌 描述 获取价格 数据表
GVT71512C18TA-6 CYPRESS 256K x 36/512K x 18 Pipelined SRAM

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GVT71512C18TA-6.7 CYPRESS 256K x 36/512K x 18 Pipelined SRAM

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GVT71512C18TA-6.7I CYPRESS 暂无描述

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GVT71512D18B-4.4 CYPRESS Cache SRAM, 512KX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

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GVT71512D18T-6.7 CYPRESS Cache SRAM, 512KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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GVT71512D18TA-6.7 CYPRESS Cache SRAM, 512KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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