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GTLP16612AA PDF预览

GTLP16612AA

更新时间: 2024-11-27 23:54:15
品牌 Logo 应用领域
其他 - ETC 总线收发器
页数 文件大小 规格书
8页 614K
描述
18-Bit Bus Transceiver

GTLP16612AA 数据手册

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GTLP16612A  
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver  
Features  
ProductDescription  
• BidirectionalinterfacebetweenGTLPandTTL  
logic levels  
PericomSemiconductor’sGTLPseriesoflogiccircuitsareproduced  
using the Company’s advanced 0.5 micron CMOS technology,  
achieving industry leading performance.  
• Designed with Edge Rate Control Circuit to  
reduce output noise  
TheGTLP16612A18-bituniversaltransceiverprovidesTTLtoGTLP  
signal level translation. The device is designed to provide high-  
speed interface between cards operating at TTL logic levels and a  
back plane operating at GTLP logic levels. High-speed back plane  
operation is a direct result of GTLP’s reduced output swing (<1V),  
reduced input threshold levels, and output edge-rate control which  
• VREF pin provides external supply reference voltage  
for receiver threshold  
• 5V tolerant inputs and outputs on A-Port  
• IncreasedB-PortDrive,50mA  
• Bus-Hold data inputs on A-Port to eliminate the need for  
pull-up resistors for unused inputs  
minimizessignalsettlingtimes.ItsfunctionissimilartoBTLorGTL  
butwithmodifieddriveroutputlevelsandreceiverthreshold.GTLP  
outputlowvoltageistypicallylessthan0.5V,theoutput highis1.5V,  
and the receiver threshold is 1.0V.  
• Power up/down high impedance  
• TTL compatible Driver and Control inputs  
• A-PortBalancedDrive: –32mA/+32mA  
• Flow-through architecture  
PinConfiguration  
• Open drain on GTLP to support wired-or connection  
• Package:  
—56-pin240MilWidePlasticTSSOP(A)  
LogicBlockDiagram  
56-Pin  
A,V  
PS8431  
09/24/99  
1

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