Datasheet > 逻辑 > 总线驱动器/收发器> GTLP16616MEA

GTLP16616MEA

更新时间： 2024-11-25 22:48:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器时钟
页数	文件大小	规格书
10页	75K
描述
17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GTLP16616MEA 数据手册

June 1997

Revised October 1998

GTLP16616

17-Bit TTL/GTLP Bus Transceiver

with Buffered Clock

General Description

Features

■ Bidirectional interface between GTLP and TTL logic

The GTLP16616 is a 17-bit registered bus transceiver that

provides TTL to GTLP signal level translation. It allows for

transparent, latched and clocked modes of data flow and

provides a buffered GTLP (CLKOUT) clock output from the

TTL CLKAB. The device provides a high speed interface

between cards operating at TTL logic levels and a back-

plane operating at GTLP logic levels. High speed back-

plane operation is a direct result of GTLP’s reduced output

swing (<1V), reduced input threshold levels and output

edge rate control. The edge rate control minimizes bus set-

tling time. GTLP is a Fairchild Semiconductor derivative of

the Gunning Transceiver logic (GTL) JEDEC standard

JESD8-3.

levels

■ Edge Rate Control to minimize noise on the GTLP port

■ Power up/down/off high impedance for live insertion

■ External V_REFpin for receiver threshold

■ CMOS technology for low power dissipation

■ 5 V tolerant inputs and outputs on the A-Port

■ Bus-hold data inputs on the A-Port eliminates the need

for external pull-up resistors on unused inputs.

■ TTL compatible driver and control inputs

■ Flow through pinout optimizes PCB layout

■ Open drain on GTLP to support wired-or connection

■ A-port source/sink −32 mA/+32 mA

Fairchild’s GTLP has internal edge-rate control and is pro-

cess, voltage, and temperature (PVT) compensated. Its

function is similar to BTL and GTL but with different output

levels and receiver threshold. GTLP output LOW level is

typically less than 0.5V, the output level HIGH is 1.5V and

the receiver threshold is 1.0V.

■ D-type flip-flop, latch and transparent data paths

■ GTLP Buffered CLKAB signal available (CLKOUT)

■ Recommended Operating Temperature −40°C to 85°C

Ordering Code:

Order Number

GTLP16616MEA

GTLP16616MTD

Package Number

MS56A

Package Description

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD56

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

DS500017.prf

www.fairchildsemi.com

12 3 4 5 6 7...10

中文翻译

下载PDF

与GTLP16616MEA相关器件

型号	品牌	获取价格	描述	数据表
GTLP16616MEAX	ETC	获取价格	Bus Transceiver
GTLP16616MTD	FAIRCHILD	获取价格	17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
GTLP16616MTDX	ETC	获取价格	Bus Transceiver
GTLP16617	FAIRCHILD	获取价格	17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
GTLP16617MEA	FAIRCHILD	获取价格	17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
GTLP16617MEAX	ETC	获取价格	Bus Transceiver
GTLP16617MTD	FAIRCHILD	获取价格	17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
GTLP16617MTDX	ETC	获取价格	Bus Transceiver
GTLP16T1655	FAIRCHILD	获取价格	16-Bit LVTTL/GTLP Universal Bus Transceiver
GTLP16T1655MTD	FAIRCHILD	获取价格	16-Bit LVTTL/GTLP Universal Bus Transceiver

与GTLP16616MEA相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

45
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

34
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

62
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

59

产品中心

服务支持

精选活动

关于我们

帮助中心

GTLP16616MEA

GTLP16616MEA 数据手册

与GTLP16616MEA相关器件

与GTLP16616MEA相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GTLP16616MEA

GTLP16616MEA 数据手册

与GTLP16616MEA相关器件

与GTLP16616MEA相关文章

您还可以找

您在本页遇到什么问题？