Datasheet > 逻辑 > 总线驱动器/收发器> GTLP16612MTD

GTLP16612MTD

更新时间： 2024-11-27 22:48:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
9页	72K
描述
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

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中文翻译

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数据手册

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GTLP16612MTD 数据手册

March 1995

Revised October 1998

GTLP16612

CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

General Description

Features

The GTLP16612 is an 18-bit universal bus transceiver

which provides TTL to GTLP signal level translation. The

device is designed to provide a high speed interface

between cards operating at TTL logic levels and a back-

plane operating at GTLP logic levels. High speed back-

plane operation is a direct result of GTLP’s reduced output

swing (<1V), reduced input threshold levels and output

edge rate control which minimizes signal settling times.

GTLP is a Fairchild Semiconductor derivative of the Gun-

ning Transceiver Logic (GTL) JEDEC standard JESD8-3.

■ Bidirectional interface between GTLP and TTL logic

levels

■ Designed with Edge Rate Control Circuit to reduce

output noise

■ V_REFpin provides external supply reference voltage for

receiver threshold

■ Submicron Core CMOS technology for low power

dissipation

■ Special PVT Compensation circuitry to provide consis-

tent performance over variations of process, supply

voltage and temperature

Fairchild’s GTLP has internal edge-rate control and is Pro-

cess, Voltage, and Temperature (PVT) compensated. Its

function is similar to BTL or GTL but with different driver

output levels and receiver threshold. GTLP output low volt-

age is typically less than 0.5V, the output high is 1.5V and

the receiver threshold is 1.0V.

■ 5V tolerant inputs and outputs on A-Port

■ Bus-Hold data inputs on A-Port to eliminate the need for

external pull-up resistors for unused inputs

■ Power up/down high impedance

■ TTL compatible Driver and Control inputs

■ A-Port outputs source/sink −32 mA/+32 mA

■ Flow-through architecture optimizes PCB layout

■ Open drain on GTLP to support wired-or connection

Ordering Code:

Order Number

GTLP16612MEA

GTLP16612MTD

Package Number

MS56A

Package Description

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD56

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

DS012390.prf

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

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与GTLP16612MTD相关器件

型号	品牌	获取价格	描述	数据表
GTLP16612MTDX	ETC	获取价格	18-Bit Bus Transceiver
GTLP16616	FAIRCHILD	获取价格	17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
GTLP16616MEA	FAIRCHILD	获取价格	17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
GTLP16616MEAX	ETC	获取价格	Bus Transceiver
GTLP16616MTD	FAIRCHILD	获取价格	17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
GTLP16616MTDX	ETC	获取价格	Bus Transceiver
GTLP16617	FAIRCHILD	获取价格	17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
GTLP16617MEA	FAIRCHILD	获取价格	17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
GTLP16617MEAX	ETC	获取价格	Bus Transceiver
GTLP16617MTD	FAIRCHILD	获取价格	17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock

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