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GS881E18BGD-250IV

更新时间： 2024-11-11 05:10:55
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
36页 1524K
描述
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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GS881E18BGD-250IV 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LBGA,
针数：165Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.64Is Samacsys：N
最长访问时间：5.5 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX18封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

GS881E18BGD-250IV 数据手册

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GS881E18/32/36B(T/D)-xxxV  
250 MHz–150 MHz  
100-Pin TQFP & 165-bump BGA  
Commercial Temp  
Industrial Temp  
512K x 18, 256K x 32, 256K x 36  
9Mb Sync Burst SRAMs  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Dual Cycle Deselect (DCD) operation  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 1.8 V or 2.5 V +10%/–10% core power supply  
• 1.8 V or 2.5 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP and 165-bump BGA  
packages  
• RoHS-compliant 100-lead TQFP and 165-bump BGA  
packages available  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
DCD Pipelined Reads  
The GS881E18/32/36B(T/D)-xxxV is a DCD (Dual Cycle  
Deselect) pipelined synchronous SRAM. SCD (Single Cycle  
Deselect) versions are also available. DCD SRAMs pipeline  
disable commands to the same degree as read commands. DCD  
RAMs hold the deselect command for one full cycle and then  
begin turning off their outputs just after the second rising edge  
of clock.  
Functional Description  
Byte Write and Global Write  
Applications  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
The GS881E18/32/36B(T/D)-xxxV is a 9,437,184-bit high  
performance synchronous SRAM with a 2-bit burst address  
counter. Although of a type originally developed for Level 2  
Cache applications supporting high performance CPUs, the  
device now finds application in synchronous SRAM  
applications, ranging from DSP main store to networking chip  
set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control  
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,  
BW, GW) are synchronous and are controlled by a positive-  
edge-triggered clock input (CK). Output enable (G) and power  
down control (ZZ) are asynchronous inputs. Burst cycles can  
be initiated with either ADSP or ADSC inputs. In Burst mode,  
subsequent burst addresses are generated internally and are  
controlled by ADV. The burst address counter may be  
configured to count in either linear or interleave order with the  
Core and Interface Voltages  
The GS881E18/32/36B(T/D)-xxxV operates on a 1.8 V or 2.5  
V power supply. All input are 2.5 V and 1.8 V compatible.  
Separate output power (V  
) pins are used to decouple  
DDQ  
output noise from the internal circuits and are 2.5 V and 1.8 V  
compatible.  
Paramter Synopsis  
-250  
-200  
-150  
Unit  
tKQ  
3.0  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x32/x36)  
200  
230  
170  
195  
140  
160  
mA  
mA  
tKQ  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x32/x36)  
160  
185  
140  
160  
128  
145  
mA  
mA  
Rev: 1.00 6/2006  
1/36  
© 2006, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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GS881E18BGD-333T GSI

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