Datasheet > GS880Z36BT-225T

GS880Z36BT-225T

更新时间： 2024-11-06 15:41:03

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
23页	684K
描述
ZBT SRAM, 256KX36, 6ns, CMOS, PQFP100, TQFP-100

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GS880Z36BT-225T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP, QFP100,.63X.87
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.67	最长访问时间：	6 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.04 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.265 mA	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GS880Z36BT-225T 数据手册

GS880Z18/36BT-250/225/200/166/150/133

100-Pin TQFP

Commercial Temp

Industrial Temp

250 MHz–133 MHz

9Mb Pipelined and Flow Through

2.5 V or 3.3 V V_DD

2.5 V or 3.3 V I/O

Synchronous NBT SRAM

Features

Functional Description

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

The GS880Z18/36BT is a 9Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

2.5 2.7 3.0 3.4 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

tCycle

Curr (x18) 280 255 230 200 185 165 mA

Curr (x36) 330 300 270 230 215 190 mA

3.3 V

2.5 V

The GS880Z18/36BT may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

Curr (x18) 275 250 230 195 180 165 mA

Curr (x36) 320 295 265 225 210 185 mA

Flow

Through

2-1-1-1

5.5 6.0 6.5 7.0 7.5 8.5 ns

tCycle

Curr (x18) 175 165 160 150 145 135 mA

Curr (x36) 200 190 180 170 165 150 mA

3.3 V

2.5 V

Curr (x18) 175 165 160 150 145 135 mA

Curr (x36) 200 190 180 170 165 150 mA

The GS880Z18/36BT is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 100-pin TQFP package.

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

Rev: 1.00b 12/2002

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

12 3 4 5 6 7...23

中文翻译

下载PDF

与GS880Z36BT-225T相关器件

型号	品牌	获取价格	描述	数据表
GS880Z36BT-250	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z36BT-250I	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z36BT-250IT	GSI	获取价格	暂无描述
GS880Z36BT-250IV	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z36BT-250IVT	GSI	获取价格	ZBT SRAM, 256KX36, 5.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-250T	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 5.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-250V	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z36BT-250VT	GSI	获取价格	ZBT SRAM, 256KX36, 5.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-250VT	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 5.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-300	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM

与GS880Z36BT-225T相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

GS880Z36BT-225T

GS880Z36BT-225T 技术参数

GS880Z36BT-225T 数据手册

与GS880Z36BT-225T相关器件

与GS880Z36BT-225T相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS880Z36BT-225T

GS880Z36BT-225T 技术参数

GS880Z36BT-225T 数据手册

与GS880Z36BT-225T相关器件

与GS880Z36BT-225T相关文章

您还可以找

您在本页遇到什么问题？