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GS880Z36CGT-200V PDF预览

GS880Z36CGT-200V

更新时间： 2024-11-26 13:48:11
品牌 Logo 应用领域
GSI /
页数 文件大小 规格书
24页 339K
描述
100 TQFP

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中文翻译

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GS880Z36CGT-200V 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
Factory Lead Time：8 weeks风险等级：5.27
其他特性：PIPELINED ARCHITECTURE, FLOW-THROUGH, IT ALSO OPERATES WITH 2.5V SUPPLYJESD-30 代码：R-XQFP-G100
长度：20 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
封装主体材料：UNSPECIFIED封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS880Z36CGT-200V 数据手册

 浏览型号GS880Z36CGT-200V的Datasheet PDF文件第2页浏览型号GS880Z36CGT-200V的Datasheet PDF文件第3页浏览型号GS880Z36CGT-200V的Datasheet PDF文件第4页浏览型号GS880Z36CGT-200V的Datasheet PDF文件第5页浏览型号GS880Z36CGT-200V的Datasheet PDF文件第6页浏览型号GS880Z36CGT-200V的Datasheet PDF文件第7页 
GS880Z18/32/36CT-xxxV  
250 MHz–150 MHz  
9Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
100-Pin TQFP  
Commercial Temp  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
rail for proper operation. Asynchronous inputs include the  
Features  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization; Fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 1.8 V or 2.5 V +10%/–10% core power supply  
• 1.8 V or 2.5 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• LBO pin for Linear or Interleave Burst mode  
• Pin compatible with 2M, 4M, and 18M devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
The GS880Z18/32/36CT-xxxV may be configured by the user  
to operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, meaning that in addition to the  
rising edge triggered registers that capture input signals, the  
device incorporates a rising-edge-triggered output register. For  
read cycles, pipelined SRAM output data is temporarily stored  
by the edge triggered output register during the access cycle  
and then released to the output drivers at the next rising edge of  
clock.  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP package available  
Functional Description  
The GS880Z18/32/36CT-xxxV is a 9Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS880Z18/32/36CT-xxxV is implemented with GSI's  
high performance CMOS technology and is available in a  
JEDEC-standard 100-pin TQFP package.  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
Parameter Synopsis  
-250  
-200  
-150  
Unit  
tKQ  
3.0  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x32/x36)  
175  
200  
150  
165  
125  
145  
mA  
mA  
tKQ  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x32/x36)  
135  
155  
125  
140  
113  
125  
mA  
mA  
Rev: 1.04 6/2012  
1/24  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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