Datasheet > GS880Z36BT-200

GS880Z36BT-200

更新时间： 2024-11-06 20:48:47

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		静态存储器内存集成电路
页数	文件大小	规格书
24页	1686K
描述
ZBT SRAM, 256KX36, 6.5ns, CMOS, PQFP100, TQFP-100

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中文翻译

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技术参数
数据手册

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GS880Z36BT-200 技术参数

生命周期：	Contact Manufacturer	包装说明：	LQFP,
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.62
最长访问时间：	6.5 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

GS880Z36BT-200 数据手册

GS880Z18/32/36BT-333/300/250/200/150

333 MHz–150 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

9Mb Pipelined and Flow Through

Synchronous NBT SRAM

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

The GS880Z18/32/36BT may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS880Z18/32/36BT is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

The GS880Z18/32/36BT is a 9Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Paramter Synopsis

-333

-300

-250

-200

-150

Unit

t_KQ

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

250

290

230

265

200

230

170

195

140

160

t_KQ

4.5

5.0

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

200

230

185

210

160

185

140

160

128

145

Rev: 1.04c 1/2012

1/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...24

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与GS880Z36BT-200相关器件

型号	品牌	获取价格	描述	数据表
GS880Z36BT-200I	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z36BT-200I	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-200IT	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-200IV	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z36BT-200IV	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-200IVT	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-200V	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880Z36BT-200VT	GSI	获取价格	ZBT SRAM, 256KX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-200VT	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS880Z36BT-225	GSI	获取价格	ZBT SRAM, 256KX36, 6ns, CMOS, PQFP100, TQFP-100

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