Datasheet > GS88018TT-80I

GS88018TT-80I

更新时间： 2024-11-21 03:12:03

品牌	Logo	应用领域
GSI		时钟静态存储器内存集成电路
页数	文件大小	规格书
25页	377K
描述
Standard SRAM, 512KX18, 14ns, CMOS, PQFP100

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技术参数
数据手册

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GS88018TT-80I 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	QFP, QFP100,.63X.87	Reach Compliance Code：	compliant
风险等级：	5.88	最长访问时间：	14 ns
最大时钟频率 (fCLK)：	66 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
内存密度：	9437184 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	18	湿度敏感等级：	3
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
最大待机电流：	0.04 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.21 mA
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	Base Number Matches：	1

GS88018TT-80I 数据手册

Preliminary

GS88018/32/36T-11/11.5/100/80/66

100-Pin TQFP

Commercial Temp

Industrial Temp

100 MHz–66 MHz

3.3 V V_DD

3.3 V and 2.5 V I/O

512K x 18, 256K x 32, 256K x 36

8Mb Sync Burst SRAMs

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipelined

operation

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

Flow Through/Pipeline Reads

The function of the Data Output Register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD Pipelined Reads

The GS88018/32/36T is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

• Automatic power-down for portable applications

• 100-lead TQFP package

-11

-11.5

-100

10 ns 12.5 ns 15 ns

5 ns

225 mA 225 mA 225 mA 200 mA 185 mA

-80

-66

Pipeline tCycle 10 ns

10 ns

Byte Write and Global Write

3-1-1-1

4.0 ns 4.0 ns 4.0 ns 4.5 ns

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Flow

Through

2-1-1-1

11 ns 11.5 ns 12 ns

15 ns 15 ns 15 ns

180 mA 180 mA 180 mA 175 mA 165 mA

14 ns

15 ns

18 ns

20 ns

tCycle

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Functional Description

Applications

Core and Interface Voltages

The GS88018/32/36T operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

The GS88018/32/36T is a 9,437,184-bit (8,388,608-bit for x32

version) high performance synchronous SRAM with a 2-bit

burst address counter. Although of a type originally developed

for Level 2 Cache applications supporting high performance

CPUs, the device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuit.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.11 9/2000

1/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...25

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与GS88018TT-80I相关器件

型号	品牌	获取价格	描述	数据表
GS88019AT-133T	GSI	获取价格	Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, TQFP-100
GS88019AT-150IT	GSI	获取价格	Cache SRAM, 512KX18, 3.3ns, CMOS, PQFP100, TQFP-100
GS88019AT-225T	GSI	获取价格	Cache SRAM, 512KX18, 2.2ns, CMOS, PQFP100, TQFP-100
GS88032AGT-133IT	GSI	获取价格	Cache SRAM, 256KX32, 8.5ns, CMOS, PQFP100, TQFP-100
GS88032AGT-133T	GSI	获取价格	Cache SRAM, 256KX32, 8.5ns, CMOS, PQFP100, TQFP-100
GS88032AGT-150I	GSI	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PQFP100, TQFP-100
GS88032AGT-166	GSI	获取价格	Cache SRAM, 256KX32, 7ns, CMOS, PQFP100, TQFP-100
GS88032AGT-166IT	GSI	获取价格	Cache SRAM, 256KX32, 7ns, CMOS, PQFP100, TQFP-100
GS88032AGT-166T	GSI	获取价格	Cache SRAM, 256KX32, 7ns, CMOS, PQFP100, TQFP-100
GS88032AGT-200	GSI	获取价格	Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, TQFP-100

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