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GS88032AT-133I PDF预览

GS88032AT-133I

更新时间： 2024-11-20 07:02:11
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
26页 734K
描述
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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GS88032AT-133I 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.78Is Samacsys：N
最长访问时间：8.5 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：8388608 bit内存集成电路类型：CACHE SRAM
内存宽度：32湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX32
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS88032AT-133I 数据手册

 浏览型号GS88032AT-133I的Datasheet PDF文件第2页浏览型号GS88032AT-133I的Datasheet PDF文件第3页浏览型号GS88032AT-133I的Datasheet PDF文件第4页浏览型号GS88032AT-133I的Datasheet PDF文件第5页浏览型号GS88032AT-133I的Datasheet PDF文件第6页浏览型号GS88032AT-133I的Datasheet PDF文件第7页 
GS88018/32/36AT-250/225/200/166/150/133  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
250 MHz–133 MHz  
512K x 18, 256K x 32, 256K x 36  
9Mb Sync Burst SRAMs  
2.5 V or 3.3 V VDD  
2.5 V or 3.3 V I/O  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Single Cycle Deselect (SCD) operation  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode pin  
low places the RAM in Flow Through mode, causing output  
data to bypass the Data Output Register. Holding FT high  
places the RAM in Pipeline mode, activating the rising-edge-  
triggered Data Output Register.  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
-250 -225 -200 -166 -150 -133 Unit  
SCD Pipelined Reads  
Pipeline  
3-1-1-1  
t
2.5 2.7 3.0 3.4 3.8 4.0 ns  
4.0 4.4 5.0 6.0 6.7 7.5 ns  
KQ  
The GS88018/32/36AT is a SCD (Single Cycle Deselect)  
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)  
versions are also available. SCD SRAMs pipeline deselect  
commands one stage less than read commands. SCD RAMs  
begin turning off their outputs immediately after the deselect  
command has been captured in the input registers.  
tCycle  
Curr (x18) 280 255 230 200 185 165 mA  
Curr (x32/x36) 330 300 270 230 215 190 mA  
3.3 V  
2.5 V  
Curr (x18) 275 250 230 195 180 165 mA  
Curr (x32/x36) 320 295 265 225 210 185 mA  
Flow  
Through  
2-1-1-1  
t
5.5 6.0 6.5 7.0 7.5 8.5 ns  
5.5 6.0 6.5 7.0 7.5 8.5 ns  
Byte Write and Global Write  
KQ  
tCycle  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Curr (x18) 175 165 160 150 145 135 mA  
Curr (x32/x36) 200 190 180 170 165 150 mA  
3.3 V  
2.5 V  
Curr (x18) 175 165 160 150 145 135 mA  
Curr (x32/x36) 200 190 180 170 165 150 mA  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Functional Description  
Applications  
The GS88018/32/36AT is a 9,437,184-bit (8,388,608-bit for  
x32 version) high performance synchronous SRAM with a  
2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Core and Interface Voltages  
The GS88018/32/36AT operates on a 2.5 V or 3.3 V power  
supply. All input are 3.3 V and 2.5 V compatible. Separate  
output power (V  
) pins are used to decouple output noise  
DDQ  
from the internal circuits and are 3.3 V and 2.5 V compatible.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
Rev: 1.02 9/2002  
1/26  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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