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GS88032AGT-133T

更新时间： 2024-11-21 05:39:55
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
24页 620K
描述
Cache SRAM, 256KX32, 8.5ns, CMOS, PQFP100, TQFP-100

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GS88032AGT-133T 数据手册

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GS88018/32/36AT-250/225/200/166/150/133  
250 MHz–133 MHz  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
512K x 18, 256K x 32, 256K x 36  
9Mb Synchronous Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Single Cycle Deselect (SCD) operation  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
SCD Pipelined Reads  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
The GS88018/32/36AT is a SCD (Single Cycle Deselect)  
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)  
versions are also available. SCD SRAMs pipeline deselect  
commands one stage less than read commands. SCD RAMs  
begin turning off their outputs immediately after the deselect  
command has been captured in the input registers.  
Functional Description  
Applications  
The GS88018/32/36AT is a 9,437,184-bit (8,388,608-bit for  
x32 version) high performance synchronous SRAM with a  
2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Controls  
Sleep Mode  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
The GS88018/32/36AT operates on a 2.5 V or 3.3 V power  
supply. All input are 3.3 V and 2.5 V compatible. Separate  
output power (V  
) pins are used to decouple output noise  
DDQ  
from the internal circuits and are 3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-250  
-225  
-200  
-166  
-150 -133 Unit  
2.5  
4.0  
2.7  
4.4  
3.0  
5.0  
3.4  
6.0  
3.8  
6.7  
4.0  
7.5  
ns  
ns  
Pipeline  
3-1-1-1  
t
KQ  
tCycle  
280  
330  
255  
300  
230  
270  
200  
230  
185  
215  
165  
190  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
Flow Through  
2-1-1-1  
t
5.5  
5.5  
6.0  
6.0  
6.5  
6.5  
7.0  
7.0  
7.5  
7.5  
8.5  
8.5  
ns  
ns  
KQ  
tCycle  
175  
200  
165  
190  
160  
180  
150  
170  
145  
165  
135  
150  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
Rev: 1.03 11/2004  
1/24  
© 2001, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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 		Cache SRAM, 256KX32, 7.5ns, CMOS, PQFP100, TQFP-100
GS88032AGT-166 GSI

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 		Cache SRAM, 256KX32, 7ns, CMOS, PQFP100, TQFP-100
GS88032AGT-166IT GSI

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 		Cache SRAM, 256KX32, 7ns, CMOS, PQFP100, TQFP-100
GS88032AGT-166T GSI

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 		Cache SRAM, 256KX32, 7ns, CMOS, PQFP100, TQFP-100
GS88032AGT-200 GSI

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 		Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, TQFP-100
GS88032AGT-200IT GSI

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 		Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, TQFP-100
GS88032AGT-225I GSI

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 		Cache SRAM, 256KX32, 6ns, CMOS, PQFP100, TQFP-100
GS88032AGT-250IT GSI

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 		Cache SRAM, 256KX32, 5.5ns, CMOS, PQFP100, TQFP-100
GS88032AT-133 GSI

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 		512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88032AT-133I GSI

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 		512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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