Datasheet > GS8672Q37AGE-375I

GS8672Q37AGE-375I

更新时间： 2024-11-20 07:46:47

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
29页	812K
描述
Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GS8672Q37AGE-375I 数据手册

浏览型号GS8672Q37AGE-375I的Datasheet PDF文件第2页

浏览型号GS8672Q37AGE-375I的Datasheet PDF文件第3页

浏览型号GS8672Q37AGE-375I的Datasheet PDF文件第4页

浏览型号GS8672Q37AGE-375I的Datasheet PDF文件第5页

浏览型号GS8672Q37AGE-375I的Datasheet PDF文件第6页

浏览型号GS8672Q37AGE-375I的Datasheet PDF文件第7页

Preliminary

GS8672Q19/37AE-400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

400 MHz–300 MHz

1.8 V V

72Mb SigmaQuad-II+

Burst of 2 ECCRAM

1.5 V I/O

Features

Clocking and Addressing Schemes

• 2.0 Clock Latency

The GS8672Q19/37AE SigmaQuad-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) outputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

future 144Mb devices

Because Separate I/O SigmaQuad-II+ B2 RAMs always

transfer data in two packets, A0 is internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfer. Because the LSB is tied off internally, the

address field of a SigmaQuad-II+ B2 RAM is always one

address pin less than the advertised index depth (e.g., the 4M x

18 has a 2M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable ECCRAMs with no On-Chip

ECC, which typically have an SER of 200 FITs/Mb or more.

SER quoted above is based on reading taken at sea level.

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad™ ECCRAM Overview

The GS8672Q19/37AE are built in compliance with the

SigmaQuad-II+ ECCRAM pinout standard for Separate I/O

synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672Q19/37AE SigmaQuad ECCRAMs

are just one element in a family of low power, low voltage

HSTL I/O ECCRAMs designed to operate at the speeds needed

to implement economical high performance networking

systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-400

2.5 ns

0.45 ns

-375

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

tKHKH

tKHQV

2.66 ns

0.45 ns

Rev: 1.00 5/2010

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...29

中文翻译

下载PDF

与GS8672Q37AGE-375I相关器件

型号	品牌	获取价格	描述	数据表
GS8672Q37AGE-400	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37AGE-400T	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37BE-300	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q37BE-300I	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q37BE-333	GSI	获取价格	JEDEC-standard pinout and package
GS8672Q37BE-333I	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q37BGE-333	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672Q37BGE-333I	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672Q37BGE-333IT	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672Q37BGE-333T	GSI	获取价格	QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

与GS8672Q37AGE-375I相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

44

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672Q37AGE-375I

GS8672Q37AGE-375I 数据手册

与GS8672Q37AGE-375I相关器件

与GS8672Q37AGE-375I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8672Q37AGE-375I

GS8672Q37AGE-375I 数据手册

与GS8672Q37AGE-375I相关器件

与GS8672Q37AGE-375I相关文章

您还可以找

您在本页遇到什么问题？