Datasheet > GS8672Q37AGE-300I

GS8672Q37AGE-300I

更新时间： 2024-11-20 05:03:23

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
29页	812K
描述
Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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GS8672Q37AGE-300I 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	17 mm	内存密度：	75497472 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	2MX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.5 mm	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15 mm	Base Number Matches：	1

GS8672Q37AGE-300I 数据手册

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Preliminary

GS8672Q19/37AE-400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

400 MHz–300 MHz

1.8 V V

72Mb SigmaQuad-II+

Burst of 2 ECCRAM

1.5 V I/O

Features

Clocking and Addressing Schemes

• 2.0 Clock Latency

The GS8672Q19/37AE SigmaQuad-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) outputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

future 144Mb devices

Because Separate I/O SigmaQuad-II+ B2 RAMs always

transfer data in two packets, A0 is internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfer. Because the LSB is tied off internally, the

address field of a SigmaQuad-II+ B2 RAM is always one

address pin less than the advertised index depth (e.g., the 4M x

18 has a 2M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable ECCRAMs with no On-Chip

ECC, which typically have an SER of 200 FITs/Mb or more.

SER quoted above is based on reading taken at sea level.

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad™ ECCRAM Overview

The GS8672Q19/37AE are built in compliance with the

SigmaQuad-II+ ECCRAM pinout standard for Separate I/O

synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672Q19/37AE SigmaQuad ECCRAMs

are just one element in a family of low power, low voltage

HSTL I/O ECCRAMs designed to operate at the speeds needed

to implement economical high performance networking

systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-400

2.5 ns

0.45 ns

-375

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

tKHKH

tKHQV

2.66 ns

0.45 ns

Rev: 1.00 5/2010

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...29

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与GS8672Q37AGE-300I相关器件

型号	品牌	获取价格	描述	数据表
GS8672Q37AGE-300IT	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37AGE-300T	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37AGE-333	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37AGE-333I	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37AGE-375I	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37AGE-400	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37AGE-400T	GSI	获取价格	Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
GS8672Q37BE-300	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q37BE-300I	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q37BE-333	GSI	获取价格	JEDEC-standard pinout and package

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