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GS8672Q36BGE-333IT PDF预览

GS8672Q36BGE-333IT

更新时间： 2024-11-19 15:33:27
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
28页 336K
描述
Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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GS8672Q36BGE-333IT 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.32最长访问时间：0.45 ns
最大时钟频率 (fCLK)：333 MHzI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165长度：17 mm
内存密度：75497472 bit内存集成电路类型：STANDARD SRAM
内存宽度：36功能数量：1
端子数量：165字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.5 mm
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：1.62 mA最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15 mm
Base Number Matches：1

GS8672Q36BGE-333IT 数据手册

 浏览型号GS8672Q36BGE-333IT的Datasheet PDF文件第2页浏览型号GS8672Q36BGE-333IT的Datasheet PDF文件第3页浏览型号GS8672Q36BGE-333IT的Datasheet PDF文件第4页浏览型号GS8672Q36BGE-333IT的Datasheet PDF文件第5页浏览型号GS8672Q36BGE-333IT的Datasheet PDF文件第6页浏览型号GS8672Q36BGE-333IT的Datasheet PDF文件第7页 
GS8672Q18/36BE-400/333/300/250/200  
400 MHz–200 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
72Mb SigmaQuad-II™  
Burst of 2 ECCRAM™  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
buffer. The device also allows the user to manipulate the  
Features  
output register clock inputs quasi independently with the C and  
C clock inputs. C and C are also independent single-ended  
clock inputs, not differential inputs. If the C clocks are tied  
High, the K clocks are routed internally to fire the output  
registers instead.  
• On-Chip ECC with virtually zero SER  
• Simultaneous Read and Write SigmaQuad™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write Capability  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
Each internal read and write operation in a SigmaQuad-II B2  
ECCRAM is two times wider than the device I/O bus. An input  
data bus de-multiplexer is used to accumulate incoming data  
before it is simultaneously written to the memory array. An  
output data multiplexer is used to capture the data produced  
from a single memory array read and then route it to the  
appropriate output drivers as needed. Therefore the address  
field of a SigmaQuad-II B2 ECCRAM is always one address  
pin less than the advertised index depth (e.g., the 4M x 18 has  
an 2M addressable index).  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• Pin-compatible with 18Mb, 36Mb, and 144Mb devices  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
SigmaQuad™ ECCRAM Overview  
The GS8672Q18/36BE SigmaQuad-II ECCRAMs are built in  
compliance with the SigmaQuad-II SRAM pinout standard for  
Separate I/O synchronous SRAMs. They are 75,497,472-bit  
(72Mb) ECCRAMs. The GS8672Q18/36BE SigmaQuad-II  
ECCRAMs are just one element in a family of Low power,  
Low voltage HSTL I/O ECCRAMs designed to operate at the  
speeds needed to implement economical High performance  
networking systems.  
On-Chip Error Correction Code  
GSI's ECCRAMs implement an ECC algorithm that detects  
and corrects all single-bit memory errors, including those  
induced by Soft Error Rate (SER) events such as cosmic rays,  
alpha particles. The resulting SER of these devices is  
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude  
improvement over comparable SRAMs with no On-Chip ECC,  
which typically have an SER of 200 FITs/Mb or more. SER  
quoted above is based on reading taken at sea level.  
Clocking and Addressing Schemes  
The GS8672Q18/36BE SigmaQuad-II ECCRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
However, the On-Chip Error Correction (ECC) will be  
disabled if a “Half Write” operation is initiated. See the Byte  
Write Contol section for further information.  
Parameter Synopsis  
-400  
2.5 ns  
0.45 ns  
-333  
3.0 ns  
0.45 ns  
-300  
3.3 ns  
0.45 ns  
-250  
4.0 ns  
0.45 ns  
-200  
5.0 ns  
0.45 ns  
tKHKH  
tKHQV  
Rev: 1.02 1/2013  
1/28  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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 		Standard SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA
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