Datasheet > GS8672Q19BE-375

GS8672Q19BE-375

更新时间： 2024-11-10 00:49:15

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
27页	475K
描述
72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM

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中文翻译

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数据手册

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GS8672Q19BE-375 数据手册

GS8672Q19/37BE-450/400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

450 MHz–300 MHz

1.8 V V

72Mb SigmaQuad -II+

1.5 V I/O

Burst of 2 ECCRAM

Features

Clocking and Addressing Schemes

• 2.0 Clock Latency

The GS8672Q19/37BE SigmaQuad-II+ ECCRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) outputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with 18Mb, 36Mb and 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Each internal read and write operation in a SigmaQuad-II+ B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B2 ECCRAM is always one address

pin less than the advertised index depth (e.g., the 4M x18 has

an 2M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable ECCRAMs with no On-Chip

ECC, which typically have an SER of 200 FITs/Mb or more.

SER quoted above is based on reading taken at sea level.

SigmaQuad™ ECCRAM Overview

The GS8672Q19/37BE are built in compliance with the

SigmaQuad-II+ ECCRAM pinout standard for Separate I/O

synchronous ECCRAMs. They are 75,497,472-bit (72Mb)

ECCRAMs. The GS8672Q19/37BE SigmaQuad ECCRAMs

are just one element in a family of low power, low voltage

HSTL I/O ECCRAMs designed to operate at the speeds needed

to implement economical high performance networking

systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-450

2.2 ns

0.45 ns

-400

-375

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

tKHKH

tKHQV

2.5 ns

2.67 ns

0.45 ns

Rev: 1.02c 8/2017

1/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...27

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与GS8672Q19BE-375相关器件

型号	品牌	获取价格	描述	数据表
GS8672Q19BE-375I	GSI	获取价格	JEDEC-standard pinout and package
GS8672Q19BE-400I	GSI	获取价格	JEDEC-standard pinout and package
GS8672Q19BE-450	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q19BGE-300	GSI	获取价格	On-Chip ECC with virtually zero SER
GS8672Q19BGE-333	GSI	获取价格	JEDEC-standard pinout and package
GS8672Q19BGE-333I	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q19BGE-375I	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q19BGE-400	GSI	获取价格	72Mb SigmaQuadTM-II Burst of 2 ECCRAMTM
GS8672Q19BGE-400I	GSI	获取价格	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8672Q19BGE-400IT	GSI	获取价格	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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