GS8662T20/38CGD-633/550/500
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
Data In
D9–D17
Don’t Care
Data In
Beat 1
Beat 2
0
1
1
0
Don’t Care
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaDDR-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaDDR-II+ SRAMs are supplied with programmable input termination on Data (DQ), Byte Write (BW), and Clock (K,
K) input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left
floating–the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination is
enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and VSS) used to
program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175 and 250. Periodic
readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner
as for driver impedance (see above).
Notes:
1. When ODT = 1, Byte Write (BW), and Clock (K, K) input termination is always enabled. Ideally, BW, K, K inputs should
always be driven High or Low. If the inputs are tri-stated, the input termination will pull the signal to VDDQ/2 (i.e., to the
switch point of the diff-amp receiver), which could cause the receiver to enter a meta-stable state, resulting in the receiver con-
suming more power than it normally would. This could result in the device’s operating currents being higher.
2. When ODT = 1, DQ input termination is enabled during Write and NOP operations, and disabled during Read operations.
Specifically, DQ input termination is disabled 0.5 cycles before the SRAM enables its DQ drivers and starts driving valid Read
Data, and remains disabled until 0.5 cycles after the SRAM stops driving valid Read Data and disables its DQ drivers; DQ
input termination is enabled at all other times. Consequently, the SRAM Controller should disable its DQ input termination,
enable its DQ drivers, and drive DQ inputs (High or Low) during Write and NOP operations. And, it should enable its DQ
input termination and disable its DQ drivers during Read operations. Care should be taken during Write or NOP -> Read
transitions, and during Read -> NOP transitions, to minimize the time during which one device (SRAM or SRAM Controller)
has enabled its DQ input termination while the other device has not yet enabled its DQ driver. Otherwise, the input termination
will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta-
stable state, resulting in the receiver consuming more power than it normally would. This could result in the device’s operating
currents being higher.
Rev: 1.01 9/2019
6/24
© 2019, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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