GS8662T20/38CGD-633/550/500
Common I/O SigmaDDR-II+ Burst of 2 SRAM Truth Table
DQ
Kn
LD
R/W
Operation
A + 0
Hi-Z / *
A + 1
1
0
0
X
0
1
Hi-Z / *
D@Kn+1
Q@Kn+3
Deselect
Write
D@Kn+1
Q@Kn+2
Read
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”.
2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.
4. When On-Die Termination is disabled (ODT = 0), DQ drivers are disabled (i.e., DQ pins are tri-stated) for one cycle in response to NOP
and Write commands, 2.5 cycles after the command is sampled.
5. When On-Die Termination is enabled (ODT = 1), DQ drivers are disabled for one cycle in response to NOP and Write commands, 2.5
cycles after the command is sampled. The state of the DQ pins during that time (denoted by “*” in the table above) is determined by the
state of the DQ input termination. See the Input Termination Impedance Control section for more information.
Burst of 2 Byte Write Clock Truth Table
BW
BW
Current Operation
D
D
K
(tn + 1
K
(tn + 1½
K
(tn)
K
(tn + 1
K
(tn + 1½)
)
)
)
Write
T
T
F
F
T
F
T
F
D1
D1
X
D2
X
Dx stored if BWn = 0 in both data transfers
Write
Dx stored if BWn = 0 in 1st data transfer only
Write
D2
X
Dx stored if BWn = 0 in 2nd data transfer only
Write Abort
No Dx stored in either data transfer
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
Rev: 1.01 9/2019
7/24
© 2019, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.