Datasheet > GS8662TT07BD-350

GS8662TT07BD-350

更新时间： 2023-11-02 19:30:12

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
29页	433K
描述
165 BGA

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GS8662TT07BD-350 数据手册

GS8662TT07/10/19/37BD-450/400/350/333/300

72Mb SigmaDDR-II+^TM

Burst of 2 SRAM

450 MHz–300 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.8 V or 1.5 V I/O

SRAMs. The GS8662TT07/10/19/37BD SigmaDDR-II+

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

Clocking and Addressing Schemes

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

The GS8662TT07/10/19/37BD SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaDDR-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore, the address field of a

SigmaDDR-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 8M x 8 has an 4M

addressable index).

SigmaDDR™ Family Overview

The GS8662TT07/10/19/37BD are built in compliance with

the SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

Parameter Synopsis

-450

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

-300

tKHKH

tKHQV

2.22 ns

0.45 ns

3.0 ns

0.45 ns

3.3 ns

0.45 ns

Rev: 1.00a 11/2011

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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