Datasheet > GS8662T20AE-300

GS8662T20AE-300

更新时间： 2024-11-28 04:55:15

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器
页数	文件大小	规格书
31页	1057K
描述
DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

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GS8662T20AE-300 数据手册

Preliminary

GS8662T20/38AE-450/400/375/333/300

450 MHz–300 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaCIO DDR-II+

Burst of 2 SRAM

1.8 V V

1.8 V and 1.5 V I/O

Features

• 2.5 Clock Latency

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and future

144Mb devices

Bottom View

165-Bump, 15 mm x 17 mm BGA

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaCIO™ Family Overview

Clocking and Addressing Schemes

The GS8662T20/38AE are built in compliance with the

SigmaCIO DDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662T20/38AE SigmaCIO SRAMs are just

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

The GS8662T20/38AE SigmaCIO DDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Common I/O x36 and x18 SigmaCIO DDR-II+ B2RAMs

always transfer data in two packets. When a new address is

loaded, A0 presets an internal 1 bit address counter. The

counter increments by 1 (toggles) for each beat of a burst of

two data transfer.

Common I/O x8 SigmaCIO DDR-II+ B2 RAMs always

transfer data in two packets. When a new address is loaded,

the LSB is internally set to 0 for the first read or write transfer,

and incremented by 1 for the next transfer. Because the LSB

is tied off internally, the address field of a x8 SigmaCIO DDR-

II+ B4 RAM is always one address pin less than the advertised

index depth (e.g., the 4M x 18 has a 2048K addressable index).

Parameter Synopsis

-450

-400

-375

-333

3.3 ns

0.45 ns

-300

3.0 ns

0.45 ns

tKHKH

tKHQV

2.22 ns

0.45 ns

2.5 ns

2.67 ns

0.45 ns

Rev: 1.00b 10/2009

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...31

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与GS8662T20AE-300相关器件

型号	品牌	获取价格	描述	数据表
GS8662T20AE-300I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-300IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-333	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-333IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-375	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-375I	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-375IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-375T	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-400T	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662T20AE-450IT	GSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

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