GS8662T20/38BD-550/500/450/400/350
GS8662T06/11BD-500/450/400/350
550 MHz–350 MHz
72Mb SigmaDDRTM-II+
Burst of 2 SRAM
165-Bump BGA
Commercial Temp
Industrial Temp
1.8 V V
DD
1.8 V or 1.5 V I/O
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Features
• 2.5 Clock Latency
TM
• Simultaneous Read and Write SigmaDDR Interface
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
Clocking and Addressing Schemes
The GS8662T06/11/20/38BD SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
• Pipelined read operation
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 8M x 8 has an 4M
addressable index).
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDR-II™ Family Overview
The GS8662T06/11/20/38BD are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662T06/11/20/38BD SigmaDDR-II+
Parameter Synopsis (x18/x36)
-550
-500
2.0 ns
0.33 ns
-450
2.2 ns
0.37 ns
-400
2.5 ns
0.45 ns
-350
tKHKH
tKHQV
1.81 ns
0.29ns
2.86 ns
0.45 ns
Parameter Synopsis (x8/x9)
-500
-450
2.2 ns
0.37ns
-400
-350
tKHKH
tKHQV
2.0 ns
2.5 ns
2.86 ns
0.45 ns
0.33 ns
0.45 ns
Rev: 1.02c 8/2017
1/31
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
5秒后页面跳转
AO3401场效应管参数、引脚图、应用原理图
BT131可控硅参数及引脚图、工作原理详解
74LS32芯片参数、引脚图及功能真值表
全球首块英伟达H200交付 黄仁勋“送货上门”
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
