GS8662Q09E-250I

更新时间： 2024-11-12 03:05:11

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
35页	1578K
描述
72Mb SigmaQuad-II Burst of 2 SRAM

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中文翻译

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数据手册
替代型号

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GS8662Q09E-250I 数据手册

Preliminary

GS8662Q08/09/18/36E-300/250/200/167

300 MHz–167 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaQuad-II

Burst of 2 SRAM

1.8 V V

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

future 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaQuad™ Family Overview

The GSQ8662Q08/09/18/36E are built in compliance with

the SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B2 RAMs always transfer

data in two packets, A0 is internally set to 0 for the first read or

write transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a SigmaQuad-II B2 RAM is always one address pin

less than the advertised index depth (e.g., the 4M x 18 has a

2048K addressable index).

Clocking and Addressing Schemes

The GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

Parameter Synopsis

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

tKHKH

tKHQV

6.0 ns

0.5 ns

Rev: 1.01 9/2005

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

中文翻译

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GS8662Q09E-250I 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1525KV18-333BZXC	CYPRESS	功能相似	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1525KV18-250BZXI	CYPRESS	功能相似	72-Mbit QDR-II SRAM 2-Word Burst Architecture

与GS8662Q09E-250I相关器件

型号	品牌	获取价格	描述	数据表
GS8662Q09E-250IT	GSI	获取价格	Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662Q09E-278I	GSI	获取价格	Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662Q09E-278T	GSI	获取价格	Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8662Q09E-300	GSI	获取价格	72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09E-300I	GSI	获取价格	72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09E-300IT	GSI	获取价格	Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X17 MM, 1 MM PITCH, FPBGA-165
GS8662Q09E-300T	GSI	获取价格	Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X17 MM, 1 MM PITCH, FPBGA-165
GS8662Q09GE-167	GSI	获取价格	72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE-167I	GSI	获取价格	72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q09GE-167T	GSI	获取价格	Standard SRAM, 8MX9, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-1

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