Datasheet > GS8662Q10BD-300MT

GS8662Q10BD-300MT

更新时间： 2024-11-13 05:42:55

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器
页数	文件大小	规格书
26页	328K
描述
DDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165

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GS8662Q07/10/19/37BD-300M

300 MHz

72Mb SigmaQuad-II+^TM

Burst of 2 SRAM

165-Bump BGA

Military Temp

1.8 V V

1.8 V and 1.5 V I/O

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Features

• Military Temperature Range

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

Clocking and Addressing Schemes

• Byte Write controls sampled at data-in time

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

The GS8662Q07/10/19/37BD SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• Pipelined read operation

Each internal read and write operation in a SigmaQuad-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore the address field of a

SigmaQuad-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 8M x 8 has an 4M

addressable index).

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

SigmaQuad™ Family Overview

The GS8662Q07/10/19/37BD are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662Q07/10/19/37BD SigmaQuad SRAMs

Parameter Synopsis

-300M

3.3 ns

tKHKH

tKHQV

0.45 ns

Rev: 1.00 10/2012

1/26

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...26

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与GS8662Q10BD-300MT相关器件

型号	品牌	获取价格	描述	数据表
GS8662Q10BD-300T	GSI	获取价格	DDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
GS8662Q10BD-333	GSI	获取价格	165 BGA
GS8662Q10BD-333I	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 2 SRAM
GS8662Q10BD-333T	GSI	获取价格	DDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
GS8662Q10BD-357	GSI	获取价格	165 BGA
GS8662Q10BD-357I	GSI	获取价格	165 BGA
GS8662Q10BGD-200	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 2 SRAM
GS8662Q10BGD-200I	GSI	获取价格	165 BGA
GS8662Q10BGD-250	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 2 SRAM
GS8662Q10BGD-250I	GSI	获取价格	165 BGA

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