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GS8662Q08BD-333I PDF预览

GS8662Q08BD-333I

更新时间: 2024-01-27 14:44:53
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
34页 677K
描述
72Mb SigmaQuad-IITM Burst of 2 SRAM

GS8662Q08BD-333I 技术参数

是否Rohs认证: 不符合生命周期:Active
零件包装代码:BGA包装说明:LBGA, BGA165,11X15,40
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
Factory Lead Time:8 weeks风险等级:5.49
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):333 MHzI/O 类型:SEPARATE
JESD-30 代码:R-PBGA-B165长度:15 mm
内存密度:67108864 bit内存集成电路类型:QDR SRAM
内存宽度:8功能数量:1
端子数量:165字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
电源:1.5/1.8,1.8 V认证状态:Not Qualified
座面最大高度:1.4 mm最小待机电流:1.7 V
子类别:SRAMs最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:13 mm

GS8662Q08BD-333I 数据手册

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GS8662Q08/09/18/36BD-357/333/300/250/200  
357 MHz–200 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
72Mb SigmaQuad-IITM  
Burst of 2 SRAM  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
Clocking and Addressing Schemes  
• Simultaneous Read and Write SigmaQuad™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
The GS8662Q08/09/18/36BD SigmaQuad-II SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer. The device also allows the user to manipulate the  
output register clock inputs quasi independently with the C and  
C clock inputs. C and C are also independent single-ended  
clock inputs, not differential inputs. If the C clocks are tied  
high, the K clocks are routed internally to fire the output  
registers instead.  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• Pin-compatible with present 144 Mb devices  
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Each internal read and write operation in a SigmaQuad-II B2  
RAM is two times wider than the device I/O bus. An input data  
bus de-multiplexer is used to accumulate incoming data before  
it is simultaneously written to the memory array. An output  
data multiplexer is used to capture the data produced from a  
single memory array read and then route it to the appropriate  
output drivers as needed. Therefore the address field of a  
SigmaQuad-II B2 RAM is always one address pin less than the  
advertised index depth (e.g., the 8M x 8 has an 4M addressable  
index).  
SigmaQuadFamily Overview  
The GS8662Q08/09/18/36BD are built in compliance with  
the SigmaQuad-II SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. The GS8662Q08/09/18/36BD SigmaQuad SRAMs  
are just one element in a family of low power, low voltage  
HSTL I/O SRAMs designed to operate at the speeds needed to  
implement economical high performance networking systems.  
Parameter Synopsis  
-357  
2.8 ns  
0.45 ns  
-333  
3.0 ns  
0.45 ns  
-300  
3.3 ns  
0.45 ns  
-250  
4.0 ns  
0.45 ns  
-200  
5.0 ns  
0.45 ns  
tKHKH  
tKHQV  
Rev: 1.02d 8/2017  
1/34  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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