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GS8640FZ18T-7.5IT PDF预览

GS8640FZ18T-7.5IT

更新时间： 2023-01-02 18:53:54
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
21页 255K
描述
ZBT SRAM, 4MX18, 7.5ns, CMOS, PQFP100, TQFP-100

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GS8640FZ18T-7.5IT 数据手册

 浏览型号GS8640FZ18T-7.5IT的Datasheet PDF文件第4页浏览型号GS8640FZ18T-7.5IT的Datasheet PDF文件第5页浏览型号GS8640FZ18T-7.5IT的Datasheet PDF文件第6页浏览型号GS8640FZ18T-7.5IT的Datasheet PDF文件第8页浏览型号GS8640FZ18T-7.5IT的Datasheet PDF文件第9页浏览型号GS8640FZ18T-7.5IT的Datasheet PDF文件第10页 
GS8640FZ18/36T-5.5/6.5/7.5/8  
Synchronous Truth Table  
Operation  
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes  
Read Cycle, Begin Burst  
Read Cycle, Continue Burst  
NOP/Read, Begin Burst  
Dummy Read, Continue Burst  
Write Cycle, Begin Burst  
Write Abort, Begin Burst  
Write Cycle, Continue Burst  
Write Abort, Continue Burst  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Continue  
Sleep Mode  
R
B
R
B
W
D
B
B
D
D
D
D
External  
Next  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
X
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
H
L
H
X
H
X
L
X
X
X
X
L
L
X
L
H
X
H
X
H
H
X
X
X
X
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
Q
Q
1,10  
2
External  
Next  
H
H
X
X
X
X
X
X
X
X
X
X
High-Z  
H
L
X
L
X
L
High-Z 1,2,10  
External  
None  
D
High-Z  
D
3
1
L
L
H
L
L
L
Next  
H
H
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
1,3,10  
Next  
H
X
X
X
X
X
X
High-Z 1,2,3,10  
High-Z  
None  
None  
L
High-Z  
None  
L
High-Z  
None  
H
X
X
X
X
X
High-Z  
High-Z  
-
1
4
None  
Clock Edge Ignore, Stall  
Current  
L-H  
Notes:  
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-  
lect cycle is executed first.  
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W  
pin is sampled low but no Byte Write pins are active so no write operation is performed.  
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during  
write cycles.  
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus  
will remain in High Z.  
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write  
signals are Low  
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.  
7. Wait states can be inserted by setting CKE high.  
8. This device contains circuitry that ensures all outputs are in High Z during power-up.  
9. A 2-bit burst counter is incorporated.  
10. The address counter is incriminated for all Burst continue cycles.  
Rev: 1.01 10/2013  
7/21  
© 2006, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1...45678910...21

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