Datasheet > GS8640FZ36GT-250IV

GS8640FZ36GT-250IV

更新时间： 2023-12-06 20:13:32

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100 TQFP

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GS8640FZ18/36GT-xxxV

6.5 ns–8.0 ns

100-Pin TQFP

Commercial Temp

Industrial Temp

72Mb Flow Through

Synchronous NBT SRAM

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

utilization of all available bus bandwidth by eliminating the

need to insert deselect cycles when the device is switched from

read to write cycles.

Features

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

flow through NtRAM™, NoBL™ and ZBT™ SRAMs

• 1.8 V or 2.5 V core power supply

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• RoHS-compliant 100-lead TQFP package

Functional Description

The GS8640FZ18/36GT-xxxV is a 72Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other flow through read/single late write SRAMs, allow

The GS8640FZ18/36GT-xxxV is implemented with GSI's

high performance CMOS technology and is available in a

JEDEC-standard 100-pin TQFP package.

Parameter Synopsis

-6.5

-7.5

-8.0

Unit

6.5

7.5

8.0

Flow Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

245

280

220

250

210

240

Rev: 1.01 7/2012

1/19

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...19

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