Datasheet > GS8640FZ18T-7.5IT

GS8640FZ18T-7.5IT

更新时间： 2023-01-02 18:53:54

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GS8640FZ18T-7.5IT 数据手册

GS8640FZ18/36T-5.5/6.5/7.5/8

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the

use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after

new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow

Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability

to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late

write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address

and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of

clock.

Rev: 1.01 10/2013

6/21

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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