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GS864036T-250IT PDF预览

GS864036T-250IT

更新时间： 2024-11-06 20:58:39
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
24页 807K
描述
Cache SRAM, 2MX36, 6.5ns, CMOS, PQFP100, TQFP-100

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GS864036T-250IT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.34最长访问时间：6.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLYJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：75497472 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS864036T-250IT 数据手册

 浏览型号GS864036T-250IT的Datasheet PDF文件第2页浏览型号GS864036T-250IT的Datasheet PDF文件第3页浏览型号GS864036T-250IT的Datasheet PDF文件第4页浏览型号GS864036T-250IT的Datasheet PDF文件第5页浏览型号GS864036T-250IT的Datasheet PDF文件第6页浏览型号GS864036T-250IT的Datasheet PDF文件第7页 
GS864018/32/36T-300/250/200/167  
300 MHz–167 MHz  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
4M x 18, 2M x 32, 2M x 36  
72Mb Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline  
operation  
• Single Cycle Deselect (SCD) operation  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP package available  
Byte Write and Global Write  
Functional Description  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Applications  
The GS864018/32/36T is a 75,497,472-bit high performance  
synchronous SRAM with a 2-bit burst address counter.  
Although of a type originally developed for Level 2 Cache  
applications supporting high performance CPUs, the device  
now finds application in synchronous SRAM applications,  
ranging from DSP main store to networking chip set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
Core and Interface Voltages  
The GS864018/32/36T operates on a 2.5 V or 3.3 V power  
supply. All input are 3.3 V and 2.5 V compatible. Separate  
output power (V  
) pins are used to decouple output noise  
DDQ  
from the internal circuits and are 3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-300  
-250  
-200  
-167  
Unit  
t
2.3  
3.3  
2.5  
4.0  
3.0  
5.0  
3.4  
6.0  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
400  
480  
340  
410  
290  
350  
260  
305  
mA  
mA  
t
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
8.0  
8.0  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
285  
330  
245  
280  
220  
250  
210  
240  
mA  
mA  
Rev: 1.03a 2/2009  
1/24  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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 		4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
GS864036T-250IVT GSI

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 		Cache SRAM, 2MX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS864036T-250T GSI

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 		Cache SRAM, 2MX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS864036T-250V GSI

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 		4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
GS864036T-250VT GSI

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 		Cache SRAM, 2MX36, 6.5ns, CMOS, PQFP100, TQFP-100
GS864036T-300 GSI

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 		4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
GS864036T-300I GSI

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 		4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
GS864036T-300IT GSI

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 		Cache SRAM, 2MX36, 5.5ns, CMOS, PQFP100, TQFP-100
GS8640E18GT-167 GSI

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 		100 TQFP
GS8640E18GT-167I GSI

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