Datasheet > GS8342T08GE-250

GS8342T08GE-250

更新时间： 2024-11-20 05:10:51

品牌	Logo	应用领域
GSI		静态存储器双倍数据速率
页数	文件大小	规格书
37页	1722K
描述
36Mb SigmaCIO DDR-II Burst of 2 SRAM

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技术参数
数据手册

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GS8342T08GE-250 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.7
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	17 mm	内存密度：	33554432 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	8
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15 mm	Base Number Matches：	1

GS8342T08GE-250 数据手册

Preliminary

GS8342T08/09/18/36E-333/300/267*/250/200/167

167 MHz–333 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

36Mb SigmaCIO DDR-II

Burst of 2 SRAM

1.8 V V

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with present 9Mb and 18Mb and future 72Mb

and 144Mb devices

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaCIO™ Family Overview

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

The GS8342T08/09/18/36E are built in compliance with the

SigmaCIO DDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342T08/09/18/36E SigmaCIO SRAMs are

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs

always transfer data in two packets. When a new address is

loaded, A0 presets an internal 1 bit address counter. The

counter increments by 1 (toggles) for each beat of a burst of

two data transfer.

Clocking and Addressing Schemes

Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer

data in two packets. When a new address is loaded, the LSB

is internally set to 0 for the first read or write transfer, and

incremented by 1 for the next transfer. Because the LSB is

tied off internally, the address field of a x8 SigmaCIO DDR-II

B4 RAM is always one address pin less than the advertised

index depth (e.g., the 8M x 8 has a 2M addressable index).

The GS8342T08/09/18/36E SigmaCIO DDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

Parameter Synopsis

-333

-300

-267*

-250

-200

-167

tKHKH

tKHQV

3.0 ns

3.3 ns

3.75 ns

4.0 ns

5.0 ns

6.0 ns

0.5 ns

0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns

* The 267 MHz speed bin is only available on the x18 part.

Rev: 1.02 8/2005

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...37

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与GS8342T08GE-250相关器件

型号	品牌	获取价格	描述	数据表
GS8342T08GE-250I	GSI	获取价格	36Mb SigmaCIO DDR-II Burst of 2 SRAM
GS8342T08GE-300	GSI	获取价格	36Mb SigmaCIO DDR-II Burst of 2 SRAM
GS8342T08GE-300I	GSI	获取价格	36Mb SigmaCIO DDR-II Burst of 2 SRAM
GS8342T08GE-333	GSI	获取价格	36Mb SigmaCIO DDR-II Burst of 2 SRAM
GS8342T08GE-333I	GSI	获取价格	36Mb SigmaCIO DDR-II Burst of 2 SRAM
GS8342T08GE-400	GSI	获取价格	Standard SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, BGA-165
GS8342T08GE-400I	GSI	获取价格	Standard SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, BGA-165
GS8342T09AE-300I	GSI	获取价格	DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8342T09AE-300IT	GSI	获取价格	DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS8342T09AE-300T	GSI	获取价格	DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

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