GS8321Z18/32/36E-xxxV
250 MHz–133 MHz
165-Bump FP-BGA
Commercial Temp
Industrial Temp
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices
• Byte write operation (9-bit Bytes)
The GS8321Z18/32/36E-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
Functional Description
The GS8321Z18/32/36E-xxxV is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
The GS8321Z18/32/36E-xxxV is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 165-bump FP-BGA package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
t
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
KQ
Pipeline
3-1-1-1
tCycle
Curr (x18) 285 265 245 220 210 185 mA
Curr (x32/x36) 350 320 295 260 240 215 mA
t
6.5 7.0 7.5 8.0 8.5 8.5 ns
6.5 7.0 7.5 8.0 8.5 8.5 ns
KQ
Flow
Through
2-1-1-1
tCycle
Curr (x18) 205 195 185 175 165 155 mA
Curr (x32/x36) 235 225 210 200 190 175 mA
Rev: 1.05 6/2006
1/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.