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GS8321Z18E-133VT PDF预览

GS8321Z18E-133VT

更新时间: 2024-11-06 06:47:55
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
33页 682K
描述
ZBT SRAM, 2MX18, 8.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

GS8321Z18E-133VT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:15 X 17 MM, 1 MM PITCH, FPBGA-165针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.89
最长访问时间:8.5 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 代码:R-PBGA-B165长度:17 mm
内存密度:37748736 bit内存集成电路类型:ZBT SRAM
内存宽度:18功能数量:1
端子数量:165字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX18封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.5 mm最大供电电压 (Vsup):2 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15 mm

GS8321Z18E-133VT 数据手册

 浏览型号GS8321Z18E-133VT的Datasheet PDF文件第2页浏览型号GS8321Z18E-133VT的Datasheet PDF文件第3页浏览型号GS8321Z18E-133VT的Datasheet PDF文件第4页浏览型号GS8321Z18E-133VT的Datasheet PDF文件第5页浏览型号GS8321Z18E-133VT的Datasheet PDF文件第6页浏览型号GS8321Z18E-133VT的Datasheet PDF文件第7页 
GS8321Z18/32/36E-xxxV  
250 MHz–133 MHz  
165-Bump FP-BGA  
Commercial Temp  
Industrial Temp  
36Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable, ZZ and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• User-configurable Pipeline and Flow Through mode  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization  
• Fully pin-compatible with both pipelined and flow through  
NtRAM™, NoBL™ and ZBT™ SRAMs  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 1.8 V or 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices  
• Byte write operation (9-bit Bytes)  
The GS8321Z18/32/36E-xxxV may be configured by the user  
to operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, in addition to the rising-edge-  
triggered registers that capture input signals, the device  
incorporates a rising-edge-triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
• 3 chip enable signals for easy depth expansion  
• ZZ pin for automatic power-down  
• JEDEC-standard 165-bump FP-BGA package  
• RoHS-compliant 165-bump BGA package available  
Functional Description  
The GS8321Z18/32/36E-xxxV is a 36Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8321Z18/32/36E-xxxV is implemented with GSI's high  
performance CMOS technology and is available in JEDEC-  
standard 165-bump FP-BGA package.  
Parameter Synopsis  
-250 -225 -200 -166 -150 -133 Unit  
t
3.0 3.0 3.0 3.5 3.8 4.0 ns  
4.0 4.4 5.0 6.0 6.6 7.5 ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18) 285 265 245 220 210 185 mA  
Curr (x32/x36) 350 320 295 260 240 215 mA  
t
6.5 7.0 7.5 8.0 8.5 8.5 ns  
6.5 7.0 7.5 8.0 8.5 8.5 ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18) 205 195 185 175 165 155 mA  
Curr (x32/x36) 235 225 210 200 190 175 mA  
Rev: 1.06 4/2008  
1/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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