Datasheet > GS8161V18AT-150IT

GS8161V18AT-150IT

更新时间： 2024-11-05 14:50:35

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
34页	715K
描述
Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, TQFP-100

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GS8161V18AT-150IT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP,
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.92	最长访问时间：	7.5 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	18874368 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.6 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

GS8161V18AT-150IT 数据手册

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Preliminary

GS8161V18A(T/D)/GS8161V32A(D)/GS8161V36A(T/D)

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

350 MHz–150 MHz

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

1.8 V V

1.8 V I/O

Flow Through/Pipeline Reads

Features

The function of the Data Output register can be controlled by the

user via the FT mode pin (Pin 14). Holding the FT mode pin low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the RAM

in Pipeline mode, activating the rising-edge-triggered Data Output

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V +10%/–10% core power supply

• 1.8 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

SCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC-standard 100-pin TQFP and 165-bump BGA packages

The GS8161V18A(T/D)/GS8161V32A(D)/GS8161V36A(T/D) is

a SCD (Single Cycle Deselect) pipelined synchronous SRAM.

DCD (Dual Cycle Deselect) versions are also available. SCD

SRAMs pipeline deselect commands one stage less than read

commands. SCD RAMs begin turning off their outputs

immediately after the deselect command has been captured in the

input registers.

Functional Description

Applications

The GS8161V18A(T/D)/GS8161V32A(D)/GS8161V36A(T/D) is

an 18,874,368-bit high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally developed

for Level 2 Cache applications supporting high performance

CPUs, the device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip set

support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Core and Interface Voltages

The GS8161V18A(T/D)/GS8161V32A(D)/GS8161V36A(T/D)

operates on a 1.8 V power supply. All input are 1.8 V compatible.

Separate output power (V_DDQ) pins are used to decouple output

noise from the internal circuits and are 1.8 V compatible.

Parameter Synopsis

-350 -333 -300 -250 -200 -150 Unit

t_KQ

tCycle

1.8

2.85

2.0

3.0

2.2

3.3

2.3

4.0

2.7

5.0

3.3

6.7

Pipeline

3-1-1-1

395

455

370

430

335

390

280

330

230

270

185

210

Curr (x18)

Curr (x32/x36)

t_KQ

tCycle

4.5

4.7

5.0

5.5

6.5

7.5

Flow

Through

2-1-1-1

270

305

250

285

230

270

210

240

185

205

170

190

Curr (x18)

Curr (x32/x36)

Rev: 1.00a 6/2003

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...34

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与GS8161V18AT-150IT相关器件

型号	品牌	获取价格	描述	数据表
GS8161V18BGD-150	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161V18BGD-150I	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161V18BGD-150IT	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161V18BGD-150T	GSI	获取价格	Cache SRAM, 1MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161V18BGD-200IT	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161V18BGD-200T	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161V18BGD-250IT	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161V18BGD-250T	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161V18BGT-200IT	GSI	获取价格	Cache SRAM, 1MX18, 6.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100
GS8161V18BGT-250I	GSI	获取价格	Cache SRAM, 1MX18, 5.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100

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