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GS8160V18CGT-300I PDF预览

GS8160V18CGT-300I

更新时间： 2024-11-07 05:10:43
品牌 Logo 应用领域
GSI 存储静态存储器
页数 文件大小 规格书
21页 560K
描述
1M x 18 and 512K x 36 18Mb Sync Burst SRAMs

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GS8160V18CGT-300I 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：5 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.6 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：PURE MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS8160V18CGT-300I 数据手册

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Preliminary  
GS8160V18/36CT-333/300/250  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
333 MHz–250 MHz  
1M x 18 and 512K x 36  
18Mb Sync Burst SRAMs  
1.8 V V  
DD  
1.8 V I/O  
cycles can be initiated with either ADSP or ADSC inputs. In  
Features  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
• FT pin for user-configurable flow through or pipeline  
operation  
• Single Cycle Deselect (SCD) operation  
• 1.8 V +10%/–10% core power supply  
• 1.8 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
• Pb-Free 100-lead TQFP package available  
Byte Write and Global Write  
Functional Description  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Applications  
The GS8160V18/36CT is an 18,874,368-bit (16,777,216-bit  
for x32 version) high performance synchronous SRAM with a  
2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Controls  
Core and Interface Voltages  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
The GS8160V18/36CT operates on a 1.8 V power supply. All  
input are 1.8 V compatible. Separate output power (V  
)
DDQ  
pins are used to decouple output noise from the internal circuits  
and are 1.8 V compatible.  
Parameter Synopsis  
-333  
-300  
-250  
Unit  
tKQ  
tCycle  
2.5  
3.0  
2.5  
3.3  
2.5  
4.0  
ns  
ns  
Pipeline  
3-1-1-1  
375  
435  
335  
390  
280  
330  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
tKQ  
4.5  
4.5  
5.0  
5.0  
5.5  
5.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
280  
335  
230  
270  
210  
240  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
Rev: 1.00 9/2004  
1/21  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...21

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与GS8160V18CGT-300I相关器件

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 		1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V18CGT-333I GSI

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GS8160V18CGT-333IT GSI

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GS8160V18CGT-333T GSI

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GS8160V18CT-250 GSI

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 		1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V18CT-250I GSI

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 		1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V18CT-300 GSI

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 		1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V18CT-300I GSI

获取价格

 		1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V18CT-333 GSI

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 		1M x 18 and 512K x 36 18Mb Sync Burst SRAMs

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