Datasheet > GS81332QT37CE-350M

GS81332QT37CE-350M

更新时间： 2024-11-13 01:12:15

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
30页	1768K
描述
Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-IITM

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Preliminary

GS82612QT19/37CE-350M/250M

GS81332QT19/37CE-350M/250M

GS8692QT19/37CE-350M/250M

350 MHz–250 MHz

Rad-Hard SRAM

165-Bump CCGA

Military Temp

1.8 V V

288Mb/144Mb/72Mb Burst of 2 SigmaQuad-II+

1.8 V and 1.5 V I/O

Features

SigmaQuad™ Family Overview

• Aerospace-Level Product

• 2.0 clock Latency

The GS82612QT19/37CE, GS81332QT19/37CE, and

GS8692QT19/37CE are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 301,989,888-bit (288Mb),

150,994,944-bit (144Mb), and 75,497,472-bit (72Mb) SRAMs.

These SigmaQuad SRAMs comprise a family of low power,

low voltage HSTL I/O Radiation-Hardened (Rad-Hard)

SRAMs designed to operate in High Radiation environments.

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

Clocking and Addressing Schemes

The Rad-Hard SigmaQuad-II+ SRAMs are synchronous

devices. They employ two input register clock inputs, K and K.

K and K are independent single-ended clock inputs, not

differential inputs to a single differential clock input buffer.

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump Ceramic Column Grid Array (CCGA) package

Each internal read and write operation in a SigmaQuad-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore, the address field of a

SigmaQuad-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 8M x 36 has an 4M

addressable index).

Radiation Performance

• Total Ionizing Dose (TID) > 200krads(Si)

• Soft Error Rate (SER) = TBR

• Neutrons = TBR

• Single Event Latchup Immunity > 80 MeV.cm /mg (100C)

Parameter Synopsis

-350M

2.86 ns

0.45 ns

-250M

4.0 ns

tKHKH

tKHQV

0.45 ns

Rev: 1.01 7/2017

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...30

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与GS81332QT37CE-350M相关器件

型号	品牌	获取价格	描述	数据表
GS81332QT37CE-350MQ	GSI	获取价格	165 CCGA
GS81332QT37CE-350MS	GSI	获取价格	165 CCGA
GS81332QT37CE-350MV	GSI	获取价格	165 CCGA
GS81332QT37LE-250MQ	GSI	获取价格	165 CLGA
GS81332QT37LE-250MS	GSI	获取价格	165 CLGA
GS81332QT37LE-250MV	GSI	获取价格	165 CLGA
GS81332QT37LE-350MQ	GSI	获取价格	165 CLGA
GS81332QT37LE-350MS	GSI	获取价格	165 CLGA
GS81332QT37LE-350MV	GSI	获取价格	165 CLGA
GS815018AB	GSI	获取价格	1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM

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