Datasheet > GS81314PQ19

GS81314PQ19

更新时间： 2024-11-13 01:11:51

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
39页	484K
描述
Burst of 2 Single-Bank ECCRAM

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数据手册

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GS81314PQ19 数据手册

GS81314PQ19/37GK-933/800

Up to 933 MHz

260-Pin BGA

Com & Ind Temp

POD I/O

144Mb SigmaQuad-IVe™

Burst of 2 Single-Bank ECCRAM™

1.2V ~ 1.3V V

DDQ

Features

Clocking and Addressing Schemes

• 4Mb x 36 and 8Mb x 18 organizations available

• Organized as a single logical memory bank

• 933 MHz maximum operating frequency

• 1.866 BT/s peak transaction rate (in billions per second)

• 134 Gb/s peak data bandwidth (in x36 devices)

• Separate I/O DDR Data Buses

The GS81314PQ19/37GK SigmaQuad-IVe ECCRAMs are

synchronous devices. They employ three pairs of positive and

negative input clocks; one pair of master clocks, CK and CK,

and two pairs of write data clocks, KD[1:0] and KD[1:0]. All

six input clocks are single-ended; that is, each is received by a

dedicated input buffer.

• Non-multiplexed DDR Address Bus

CK and CK are used to latch address and control inputs, and to

control all output timing. KD[1:0] and KD[1:0] are used solely

to latch data inputs.

• Two operations - Read and Write - per clock cycle

• No address/bank restrictions on Read and Write ops

• Burst of 2 Read and Write operations

• 5 cycle Read Latency

• On-chip ECC with virtually zero SER

• Loopback signal timing training capability

• 1.2V ~ 1.3V nominal core voltage

Each internal read and write operation in a SigmaQuad-IVe B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaQuad-IVe B2 ECCRAM is always one address

pin less than the advertised index depth (e.g. the 8M x 18 has

4M addressable index).

• 1.2V ~ 1.3V POD I/O interface

• Configuration registers

• Configurable ODT (on-die termination)

• ZQ pin for programmable driver impedance

• ZT pin for programmable ODT impedance

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-

compliant BGA package

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by SER events such as cosmic rays, alpha particles,

etc. The resulting Soft Error Rate of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no on-chip ECC,

which typically have an SER of 200 FITs/Mb or more.

SigmaQuad-IVe™ Family Overview

SigmaQuad-IVe ECCRAMs are the Separate I/O half of the

SigmaQuad-IVe/SigmaDDR-IVe family of high performance

ECCRAMs. Although similar to GSI's third generation of

networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe

family), these fourth generation devices offer several new

features that help enable significantly higher performance.

All quoted SER values are at sea level in New York City.

Parameter Synopsis

Speed Grade

Max Operating Frequency

Read Latency

-933

-800

933 MHz

800 MHz

5 cycles

1.25V to 1.35V

1.15V to 1.35V

Rev: 1.02 3/2016

1/39

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...39

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与GS81314PQ19相关器件

型号	品牌	获取价格	描述	数据表
GS81314PQ19GK-800	GSI	获取价格	Burst of 2 Single-Bank ECCRAM
GS81314PQ19GK-800I	GSI	获取价格	Burst of 2 Single-Bank ECCRAM
GS81314PQ36GK-106	GSI	获取价格	Burst of 2 Multi-Bank ECCRAM
GS81314PQ36GK-120I	GSI	获取价格	Burst of 2 Multi-Bank ECCRAM
GS81314PQ36GK-133I	GSI	获取价格	Burst of 2 Multi-Bank ECCRAM
GS81314PT18	GSI	获取价格	144Mb SigmaDDR-IVeâ¢ Burst of 2 Single-Bank
GS81332DT19CE-250MQ	GSI	获取价格	165 CCGA
GS81332DT19CE-250MS	GSI	获取价格	165 CCGA
GS81332DT19CE-250MV	GSI	获取价格	165 CCGA
GS81332DT19CE-350MQ	GSI	获取价格	165 CCGA

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